MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
16 Freescale Semiconductor
DDR2 SDRAM
MCS output hold with respect to MCK t
DDKHCX
ns 3
266 MHz 2.5 —
MCK to MDQS Skew t
DDKHMH
–0.6 0.6 ns 4
MDQ/MDM output setup with respect to MDQS t
DDKHDS,
t
DDKLDS
ns 5
266 MHz 0.9 —
MDQ/MDM output hold with respect to MDQS t
DDKHDX,
t
DDKLDX
ps 5
266 MHz 1100 —
MDQS preamble start t
DDKHMP
0.75 x t
MCK
—ns6
MDQS epilogue end t
DDKHME
0.4 x t
MCK
0.6 x t
MCK
ns 6
Notes:
1. The symbols used for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state)(reference)(state)
for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t
DDKHAS
symbolizes DDR timing (DD) for the time t
MCK
memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, t
DDKLDX
symbolizes DDR timing (DD) for the time t
MCK
memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK
, MCS, and MDQ/MDM/MDQS. For the ADDR/CMD
setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks by 1/2 applied
cycle.
4. Note that t
DDKHMH
follows the symbol conventions described in note 1. For example, t
DDKHMH
describes the DDR timing (DD)
from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). t
DDKHMH
can be modified through control
of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjusts in the
CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. See the MPC
8306S PowerQUICC II Pro Integrated Communications Processor Family Reference
Manual for a description and understanding of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), or data
mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. t
DDKHMP
follows the symbol conventions described in note 1.
Table 16. DDR2 SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions with GV
DD
of 1.8V ± 100mV.
Parameter Symbol
1
Min Max Unit Note
