MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor 39
SPI
17.2 SPI AC Timing Specifications
The following table and provide the SPI input and output AC timing specifications.
The following figure provides the AC test load for the SPI.
Figure 29. SPI AC Test Load
Figure 30 and Figure 31 represent the AC timing from Table 43. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Table 42. SPI DC Electrical Characteristics
Characteristic Symbol Condition Min Max Unit
Output high voltage V
OH
I
OH
= –6.0 mA 2.4 — V
Output low voltage V
OL
I
OL
= 6.0 mA — 0.5 V
Output low voltage V
OL
I
OL
= 3.2 mA — 0.4 V
Input high voltage V
IH
— 2.0 OV
DD
+0.3 V
Input low voltage V
IL
—–0.30.8V
Input current I
IN
0 V V
IN
OV
DD
— ±5 A
Table 43. SPI AC Timing Specifications
1
Characteristic Symbol
2
Min Max Unit
SPI outputs—Master mode (internal clock) delay t
NIKHOV
0.5 6 ns
SPI outputs—Slave mode (external clock) delay t
NEKHOV
28ns
SPI inputs—Master mode (internal clock) input setup time t
NIIVKH
6—ns
SPI inputs—Master mode (internal clock) input hold time t
NIIXKH
0—ns
SPI inputs—Slave mode (external clock) input setup time t
NEIVKH
4—ns
SPI inputs—Slave mode (external clock) input hold time t
NEIXKH
2—ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state)(reference)(state)
for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
NIKHOV
symbolizes the NMSI
outputs internal timing (NI) for the time t
SPI
memory clock reference (K) goes from the high state (H) until outputs (O) are
valid (V).
3. All units of output delay must be enabled for 8306S output port spimosi (SPI Master Mode)
4. delay units must not be enabled for Slave Mode.
Output
Z
0
= 50
OV
DD
/2
R
L
= 50
