MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor 65
System Design Information
22.2 PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins. The voltage
level at each AV
DD
n
pin should always be equivalent to V
DD
, and preferably these voltages are derived
directly from V
DD
through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits as illustrated in Figure 41, one to each of the three AV
DD
pins. By
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum effective series inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV
DD
pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
DD
pin, which is on the periphery of package, without the inductance of vias.
The following figure shows the PLL power supply filter circuit.
Figure 41. PLL Power Supply Filter Circuit
22.3 Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the MPC8306S can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8306S system, and MPC8306S
itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system
designer place at least one decoupling capacitor at each V
DD
, OV
DD
, and GV
DD
pins of the MPC8306S.
These decoupling capacitors should receive their power from separate V
DD
, OV
DD
, GV
DD
, and GND
power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly
under the device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V
DD
, OV
DD
, and GV
DD
planes, to enable quick recharging of the smaller chip capacitors.
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick
response time necessary. They should also be connected to the power and ground planes through two vias
V
DD
AV
DD
2.2 µF 2.2 µF
GND
Low ESL Surface Mount Capacitors (<0.5 nH)
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