MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor 35
I
2
C
The following figure provides the AC test load for the I
2
C.
Figure 25. I
2
C AC Test Load
The following figure shows the AC timing diagram for the I
2
C bus.
Figure 26. I
2
C Bus AC Timing Diagram
Fall time of both SDA and SCL signals
t
I2CF
20 + 0.1 C
B
4
300 ns
Setup time for STOP condition t
I2PVKH
0.6 — s
Bus free time between a STOP and START condition t
I2KHDX
1.3 — s
Noise margin at the LOW level for each connected device (including
hysteresis)
V
NL
0.1 OV
DD
—V
Noise margin at the HIGH level for each connected device (including
hysteresis)
V
NH
0.2 OV
DD
—V
Notes:
1. The symbols used for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state)(reference)(state)
for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
I2DVKH
symbolizes I
2
C timing (I2)
with respect to the time data input signals (D) reach the valid state (V) relative to the t
I2C
clock reference (K) going to the high
(H) state or setup time. Also, t
I2SXKL
symbolizes I
2
C timing (I2) for the time that the data with respect to the start condition
(S) went invalid (X) relative to the t
I2C
clock reference (K) going to the low (L) state or hold time. Also, t
I2PVKH
symbolizes I
2
C
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t
I2C
clock
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. MPC8306S provides a hold time of at least 300 ns for the SDA signal (referred to the V
IH
(min) of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
3. The maximum t
I2DVKL
has only to be met if the device does not stretch the LOW period (t
I2CL
) of the SCL signal.
4. C
B
= capacitance of one bus line in pF.
Table 35. I
2
C AC Electrical Specifications (continued)
All values refer to V
IH
(min) and V
IL
(max) levels (see Tab le 3 4 ).
Parameter Symbol
1
Min Max Unit
Output
Z
0
= 50
OV
DD
/2
R
L
= 50
SrS
SDA
SCL
t
I2CF
t
I2SXKL
t
I2CL
t
I2CH
t
I2DXKL
t
I2DVKH
t
I2SXKL
t
I2SVKH
t
I2KHKL
t
I2PVKH
t
I2CR
t
I2CF
PS
