ADF4360-4BCPZRL7 Datasheet ADF4360-4BCPZRL7, ADF4360-4BCPZ, ADF4360-4BCPZRL | P19-P21

ADF4360-4 Data Sheet

Rev. C | Page 18 of 24

CONTROL LATCH

With (C2, C1) = (0, 0), the control latch is programmed. Table 7

shows the input data format for programming the control latch.

Prescaler Value

For the ADF4360-4, P2 and P1 in the control latch set the pre-

scaler values.

Power-Down

DB21 (PD2) and DB20 (PD1) provide programmable pow-

erdown modes.

In the programmed asynchronous power-down, the device

powers down immediately after latching a 1 into Bit PD1, with

the condition that PD2 has been loaded with a 0. In the pro-

grammed synchronous power-down, the device power-down is

gated by the charge pump to prevent unwanted frequency

jumps. Once the power-down is enabled by writing a 1 into

Bit PD1 (on the condition that a 1 has also been loaded to PD2),

the device goes into power-down on the second rising edge of

the R counter output, after LE goes high. When the CE pin is

low, the device is immediately disabled regardless of the state of

PD1 or PD2.

When a power-down is activated (either synchronous or

asynchronous mode), the following events occur:

• All active dc current paths are removed.

• The R, N, and timeout counters are forced to their load

state conditions.

• The charge pump is forced into three-state mode.

• The digital lock detect circuitry is reset.

• The RF outputs are debiased to a high impedance state.

• The reference input buffer circuitry is disabled.

• The input register remains active and capable of loading

and latching data.

Charge Pump Currents

CPI3, CPI2, and CPI1 in the ADF4360-4 determine

Current Setting 1.

CPI6, CPI5, and CPI4 determine Current Setting 2. See the

truth table in Table 7.

Output Power Level

Bits PL1 and PL2 set the output power level of the VCO. See the

truth table in Table 7.

Mute-Till-Lock Detect

DB11 of the control latch in the ADF4360-4 is the mute-till-lock

detect bit. This function, when enabled, ensures that the RF outputs

are not switched on until the PLL is locked.

CP Gain

DB10 of the control latch in the ADF4360-4 is the charge pump

gain bit. When it is programmed to a 1, Current Setting 2 is

used. When it is programmed to a 0, Current Setting 1 is used.

Charge Pump Three-State

This bit puts the charge pump into three-state mode when

programmed to a 1. It should be set to 0 for normal operation.

Phase Detector Polarity

The PDP bit in the ADF4360-4 sets the phase detector polarity.

The positive setting enabled by programming a 1 is used when

using the on-chip VCO with a passive loop filter or with an

active noninverting filter. It can also be set to 0. This is required,

if an active inverting loop filter is used.

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, and M1.

See the truth table in Table 7.

Counter Reset

DB4 is the counter reset bit for the ADF4360-4. When this is 1,

the R counter and the A, B counters are reset. For normal oper-

ation, this bit should be 0.

Core Power Level

PC1 and PC2 set the power level in the VCO core. The recom-

mended setting is 15 mA. See the truth table in Table 7.

Data Sheet ADF4360-4

Rev. C | Page 19 of 24

N COUNTER LATCH

With (C2, C1) = (1, 0), the N counter latch is programmed.

Table 8 shows the input data format for programming the

N counter latch.

A Counter Latch

A5 to A1 program the 5-bit A counter. The divide range is 0

(00000) to 31 (11111).

Reserved Bits

DB7 is a spare bit that is reserved. It should be programmed to 0.

B Counter Latch

B13 to B1 program the B counter. The divide range is 3

(00.....0011) to 8191 (11....111).

Overall Divide Range

The overall divide range is defined by ((P × B) + A), where P is

the prescaler value.

CP Gain

DB21 of the N counter latch in the ADF4360-4 is the charge

pump gain bit. When this is programmed to 1, Current Setting 2

is used. When programmed to 0, Current Setting 1 is used. This bit

can also be programmed through DB10 of the control latch. The bit

always reflects the latest value written to it, whether this is through

the control latch or the N counter latch.

Divide-by-2

DB22 is the divide-by-2 bit. When set to 1, the output divide-by-2

function is chosen. When it is set to 0, normal operation occurs.

Divide-by-2 Select

DB23 is the divide-by-2 select bit. When programmed to 1, the

divide-by-2 output is selected as the prescaler input. When set

to 0, the fundamental is used as the prescaler input. For exam-

ple, using the output divide-by-2 feature and a PFD frequency

of 200 kHz, the user needs a value of N = 8000 to generate

800 MHz. With the divide-by-2 select bit high, the user may

keep N = 4000.

R COUNTER LATCH

With (C2, C1) = (0, 1), the R counter latch is programmed.

Table 9 shows the input data format for programming the

R counter latch.

R Counter

R1 to R14 set the counter divide ratio. The divide range is 1

(00......001) to 16383 (111......111).

Antibacklash Pulse Width

DB16 and DB17 set the antibacklash pulse width.

Lock Detect Precision

DB18 is the lock detect precision bit. This bit sets the number of

reference cycles with less than 15 ns phase error for entering the

locked state. With LDP at 1, five cycles are taken; with LDP at 0,

three cycles are taken.

Test Mode Bit

DB19 is the test mode bit (TMB) and should be set to 0. With

TMB = 0, the contents of the test mode latch are ignored and

normal operation occurs as determined by the contents of the

control latch, R counter latch, and N counter latch. Note that

test modes are for factory testing only and should not be pro-

grammed by the user.

Band Select Clock

These bits set a divider for the band select logic clock input. The

output of the R counter is by default the value used to clock the

band select logic, but, if this value is too high (>1 MHz), a

divider can be switched on to divide the R counter output to a

smaller value (see Table 9).

Reserved Bits

DB23 to DB22 are spare bits that are reserved. They should be

programmed to 0.

ADF4360-4 Data Sheet

Rev. C | Page 20 of 24

APPLICATIONS INFORMATION

DIRECT CONVERSION MODULATOR

Direct conversion architectures are increasingly being used to

implement base station transmitters. Figure 17 shows how Ana-

log Devices, Inc., devices can be used to implement such a system.

The circuit block diagram shows the AD9761 TxDAC® being

used with the AD8349. The use of dual integrated DACs, such

as the AD9761 with its specified ±0.02 dB and ±0.004 dB gain

and offset matching characteristics, ensures minimum error

contribution (over temperature) from this portion of the

signal chain.

The local oscillator is implemented using the ADF4360-4. The

low-pass filter was designed using ADIsimPLL for a channel

spacing of 200 kHz and an open-loop bandwidth of 10 kHz.

The LO ports of the AD8349 can be driven differentially from

the complementary RF

OUT

A and RF

OUT

B outputs of the

ADF4360-4. This gives better performance than a single-ended

LO driver and eliminates the often necessary use of a balun to

convert from a single-ended LO input to the more desirable

differential LO inputs for the AD8349. The typical rms phase

noise (100 Hz to 100 kHz) of the LO in this configuration is 1.09°.

The AD8349 accepts LO drive levels from −10 dBm to 0 dBm.

The optimum LO power can be software programmed on the

ADF4360-4, which allows levels from −13 dBm to −4 dBm from

each output.

The RF output is designed to drive a 50 Ω load but must be ac-

coupled, as shown in Figure 17. If the I and Q inputs are driven

in quadrature by 2 V p-p signals, the resulting output power

from the modulator is approximately 2 dBm.

AD9761

TxDAC

AD8349

REFIO

FSADJ

MODULATED

DIGITAL

DATA

QOUTB

IOUTA

IOUTB

QOUTA

2kΩ

LOW-PASS

FILTER

LOW-PASS

FILTER

SPI COMPATIBLE SERIAL BUS

ADF4360-4

VCO

CPGND AGND DGND

OUT

1nF

1nF 330pF

12nF

47nH 47nH

1.8pF

100pF

RF PA

5.1nH

1nF1nF

4.7kΩ

6.8kΩ

3.9kΩ

SET

DATA

CLK

REF

FREF

TUNE

CE MUXOUT

VPS1

IBBP

IBBN

QBBP

QBBN

LOIP

LOIN

VPS2

2023221

1 3

8 9 10 11 22 15

LOCK

DETECT

PHASE

SPLITTER

04438-021

51Ω

10µF

Figure 17. Direct Conversion Modulator

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

ADF4360-4BCPZRL7

Mfr. #:

Buy ADF4360-4BCPZRL7

Manufacturer:

Analog Devices Inc.

Description:

Phase Locked Loops - PLL Intg Integer-N VCO Out Freq 1450-1750

Lifecycle:

New from this manufacturer.

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ADF4360-4BCPZRL7

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