TLP2200
2014-09-01 4
Switching Characteristics
(unless otherwise specified, Ta = 0~85°C,V
CC
= 4.5~20V,I
F(ON)
= 1.6~5mA,I
F(OFF)
= 0~0.1mA)
Characteristic Symbol
Test
Circuit
Test Condition Min Typ. Max Unit
Propagation delay time to
logic high output level
(Note 5)
t
pLH
1
Without peaking capacitor
C
1
― 235 ―
ns
With peaking capacitor C
1
― ― 400
Propagation delay time to
logic low output level
(Note 5)
t
pHL
Without peaking capacitor
C
1
― 250 ―
ns
With peaking capacitor C
1
― ― 400
Output rise time (10−90%) t
―
― 35 ― ns
Output fall time (90−10%) t
― 20 ― ns
Output enable time to
logic high
t
pZH
2
―
― ― ― ns
Output enable time to
logic low
t
pZL
―
― ― ― ns
Output disable time from
logic high
t
pHZ
―
― ― ― ns
Output disable time from
logic low
t
pLZ
―
― ― ― ns
Common mode transient
immunity at logic high
output (Note 6)
CM
H
3
I
F
= 1.6mA, V
CM
= 50V,
Ta = 25°C
−1000 ― ― V / μs
Common mode transient
immunity at logic low
output (Note 6)
CM
L
I
F
= 0mA, V
CM
= 50V,
Ta = 25°C
1000
―
― V / μs
(*) All typ. values are at Ta = 25°C, V
CC
= 5V, I
F(ON)
= 3mA unless otherwise specified.
(Note 4) Duration of output short circuit time should not exceed 10ms.
(Note 5) The t
pLH
propagation delay is measured from the 50% point on the leading edge of the input pulse to the
1.3V point on the leading edge of the output pulse.
The t
pHL
propagation delay is measured from the 50% point on the trailing edge of the input pulse to the
1.3V point on the trailing edge of the output pulse.
(Note 6) CM
L
is the maximum rate of rise of the common mode voltage that can be sustained with the output
voltage in the logic low state (V
O
≤ 0.8V).
CM
H
is the maximum rate of fall of the common mode voltage that can be sustained with the output
voltage in the logic high state (V
O
≤ 2.0V).
