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NCP3063DFBSTGEVB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
NCP3063, NCP3063B, NCV3063
http://onsemi.com
7
INTRODUCTION
The NCP3063 is a monolithic power switching regulator
optimized for dc to dc converter applications. The
combination of its features enables the system designer to
directly implement step−up, step−down, and voltage−
inverting converters with a minimum number of external
components. Potential applications include cost sensitive
consumer products as well as equipment for industrial
markets. A representative block diagram is shown in
Figure 4.
Operating Description
The NCP3063 is a hysteretic, dc−dc converter that uses a
gated oscillator to regulate output voltage. In general, this
mode of operation is somewhat analogous to a capacitor
charge pump and does not require dominant pole loop
compensation for converter stability. The Typical Operating
Waveforms are shown in Figure 14. The output voltage
waveform shown is for a step−down converter with the
ripple and phasing exaggerated for clarity. During initial
converter startup, the feedback comparator senses that the
output voltage level is below nominal. This causes the
output switch to turn on and off at a frequency and duty cycle
controlled by the oscillator, thus pumping up the output filter
capacitor. When the output voltage level reaches nominal,
the output switch next cycle turning on is inhibited. The
feedback comparator will enable the switching immediately
when the load current causes the output voltage to fall below
nominal. Under these conditions, output switch conduction
can be enabled for a partial oscillator cycle, a partial cycle
plus a complete cycle, multiple cycles, or a partial cycle plus
multiple cycles. (See AN920/D for more information).
Oscillator
The oscillator frequency and off−time of the output switch
are programmed by the value selected for timing capacitor
C
T
. Capacitor C
T
is charged and discharged by a 1 to 6 ratio
internal current source and sink, generating a positive going
sawtooth waveform at Pin 3. This ratio sets the maximum
t
ON
/(t
ON
+ t
OFF
) of the switching converter as 6/(6 + 1) or
0.857 (typical) The oscillator peak and valley voltage
difference is 500 mV typically. To calculate the C
T
capacitor
value for required oscillator frequency, use the equations
found in Figure 15. An Excel based design tool can be found
at www.onsemi.com on the NCP3063 product page.
Figure 14. Typical Operating Waveforms
1
0
Output Switch
1
0
On
Off
Feedback Comparator Output
Nominal Output Voltage Level
Startup Operation
Output Voltage
Timing Capacitor, C
T
I
PK
Comparator Output
NCP3063, NCP3063B, NCV3063
http://onsemi.com
8
Peak Current Sense Comparator
With a voltage ripple gated converter operating under
normal conditions, output switch conduction is initiated by
the Voltage Feedback comparator and terminated by the
oscillator. Abnormal operating conditions occur when the
converter output is overloaded or when feedback voltage
sensing is lost. Under these conditions, the I
pk
Current Sense
comparator will protect the Darlington output Switch. The
switch current is converted to a voltage by inserting a
fractional ohm resistor, R
SC
, in series with V
CC
and the
Darlington output switch. The voltage drop across R
SC
is
monitored by the Current Sense comparator. If the voltage
drop exceeds 200 mV with respect to V
CC
, the comparator
will set the latch and terminate output switch conduction on
a cycle−by−cycle basis. This Comparator/Latch
configuration ensures that the Output Switch has only a
single on−time during a given oscillator cycle.
Real
V
turn−off
on
R
s
Resistor
t_delay
I1
Io
di/dt slope
I through the
Darlington
Switch
V
ipk(sense)
The V
IPK(Sense)
Current Limit Sense Voltage threshold is
specified at static conditions. In dynamic operation the
sensed current turn−off value depends on comparator
response time and di/dt current slope.
Real V
turn−off
on R
sc
resistor
V
turn_off
+ V
ipk(sense)
) Rs @ (t_delay @ dińdt)
Typical I
pk
comparator response time t_delay is 350 ns.
The di/dt current slope is growing with voltage difference on
the inductor pins and with decreasing inductor value.
It is recommended to check the real max peak current in
the application at worst conditions to be sure that the max
peak current will never get over the 1.5 A Darlington Switch
Current max rating.
Thermal Shutdown
Internal thermal shutdown circuitry is provided to protect
the IC in the event that the maximum junction temperature
is exceeded. When activated, typically at 160°C, the Output
Switch is disabled. The temperature sensing circuit is
designed with 10°C hysteresis. The Switch is enabled again
when the chip temperature decreases to at least 150°C
threshold. This feature is provided to prevent
catastrophic failures from accidental device
overheating. It is not intended to be used as a
replacement for proper heatsinking.
Output Switch
The output switch is designed in a Darlington
configuration. This allows the application designer to
operate at all conditions at high switching speed and low
voltage drop. The Darlington Output Switch is designed to
switch a maximum of 40 V collector to emitter voltage and
current up to 1.5 A.
APPLICATIONS
Figures 16 through 24 show the simplicity and flexibility
of the NCP3063. Three main converter topologies are
demonstrated with actual test data shown below each of the
circuit diagrams.
Figure 15 gives the relevant design equations for the key
parameters. Additionally, a complete application design aid
for the NCP3063 can be found at www.onsemi.com.
Figures 25 through 31 show typical NCP3063
applications with external transistors. This solution helps to
increase output current and helps with efficiency still
keeping low cost bill of materials. Typical schematics of
boost configuration with NMOS transistor, buck
configuration with PMOS transistor and buck configuration
with LOW V
CE(sat)
PNP are shown.
Another advantage of using the external transistor is
higher operating frequency which can go up to 250 kHz.
Smaller size of the output components such as inductor and
capacitor can be used then.
NCP3063, NCP3063B, NCV3063
http://onsemi.com
9
(See Notes 9, 10, 11)
Step−Down Step−Up Voltage−Inverting
t
on
t
off
V
out
) V
F
V
in
* V
SWCE
* V
out
V
out
) V
F
* V
in
V
in
* V
SWCE
|V
out
| ) V
F
V
in
* V
SWCE
t
on
t
on
t
off
f
ǒ
t
on
t
off
) 1
Ǔ
t
on
t
off
f
ǒ
t
on
t
off
) 1
Ǔ
t
on
t
off
f
ǒ
t
on
t
off
) 1
Ǔ
C
T
C
T
+
381.6 @ 10
*6
f
osc
* 343 @ 10
*12
I
L(avg)
I
out
I
out
ǒ
t
on
t
off
) 1
Ǔ
I
out
ǒ
t
on
t
off
) 1
Ǔ
I
pk
(Switch)
I
L(avg)
)
DI
L
2
I
L(avg)
)
DI
L
2
I
L(avg)
)
DI
L
2
R
SC
0.20
I
pk (Switch)
0.20
I
pk (Switch)
0.20
I
pk (Switch)
L
ǒ
V
in
* V
SWCE
* V
out
DI
L
Ǔ
t
on
ǒ
V
in
* V
SWCE
DI
L
Ǔ
t
on
ǒ
V
in
* V
SWCE
DI
L
Ǔ
t
on
V
ripple(pp)
DI
L
ǒ
1
8 f C
O
Ǔ
2
) (ESR)
2
Ǹ
[
t
on
I
out
C
O
) DI
L
@ ESR [
t
on
I
out
C
O
) DI
L
@ ESR
V
out
V
TH
ǒ
R
2
R
1
) 1
Ǔ
V
TH
ǒ
R
2
R
1
) 1
Ǔ
V
TH
ǒ
R
2
R
1
) 1
Ǔ
9. V
SWCE
− Darlington Switch Collector to Emitter Voltage Drop, refer to Figures 7, 8, 9 and 10.
10.V
F
− Output rectifier forward voltage drop. Typical value for 1N5819 Schottky barrier rectifier is 0.4 V.
11. The calculated t
on
/t
off
must not exceed the minimum guaranteed oscillator charge to discharge ratio.
The Following Converter Characteristics Must Be Chosen:
V
in
− Nominal operating input voltage.
V
out
− Desired output voltage.
I
out
− Desired output current.
DI
L
− Desired peak−to−peak inductor ripple current. For maximum output current it is suggested that DI
L
be chosen to be
less than 10% of the average inductor current I
L(avg)
. This will help prevent I
pk
(Switch)
from reaching the current limit threshold
set by R
SC
. If the design goal is to use a minimum inductance value, let DI
L
= 2(I
L(avg)
). This will proportionally reduce
converter output current capability.
f − Maximum output switch frequency.
V
ripple(pp)
− Desired peak−to−peak output ripple voltage. For best performance the ripple voltage should be kept to a low
value since it will directly affect line and load regulation. Capacitor C
O
should be a low equivalent series resistance (ESR)
electrolytic designed for switching regulator applications.
Figure 15. Design Equations
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

NCP3063DFBSTGEVB

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