AD7868
–4–
REV. B
Limit at T
MIN
, T
MAX
Limit at T
MIN
, T
MAX
Parameter (A, B Versions) (T Version) Units Conditions/Comments
ADC TIMING
t
1
50 50 ns min CONVST Pulse Width
t
2
3
440 440 ns min RCLK Cycle Time, Internal Clock
t
3
100 100 ns min RFS to RCLK Falling Edge Setup Time
t
4
20 20 ns min RCLK Rising Edge to RFS
100 100 ns max
t
5
4
155 155 ns max RCLK to Valid Data Delay, C
L
= 35 pF
t
6
4 4 ns min Bus Relinquish Time after RCLK
100 100 ns max
t
13
5
2 RCLK +200 to 2 RCLK +200 to ns typ CONVST to RFS Delay
3 RCLK + 200 3 RCLK + 200
DAC TIMING
t
7
50 50 ns min TFS to TCLK Falling Edge
t
8
75 100 ns min TCLK Falling Edge to TFS
t
9
6
150 200 ns min TCLK Cycle Time
t
10
30 40 ns min Data Valid to TCLK Setup Time
t
11
75 100 ns min Data Valid to TCLK Hold Time
t
12
40 40 ns min LDAC Pulse Width
NOTES
1
Timing specifications are sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a
voltage level of 1.6 V.
2
Serial timing is measured with a 4.7 kΩ pull-up resistor on DR and RFS and a 2 kΩ pull-up resistor on RCLK . The capacitance on all three output is 35 pF.
3
When using internal clock, RCLK mark/space ratio (measured from a voltage level of 1.6 V) range is 40/60 to 60/40. For external clock, RCLK mark/space ratio =
external clock mark/space ratio.
4
DR will drive higher capacitance loads but this will add to t
5
since it increases the external RC time constant (4.7 kΩ/C
L
) and hence the time to reach 2.4 V.
5
Time 2 RCLK to 3 RCLK depends on conversion start to ADC clock synchronization.
6
TCLK mark/space ratio is 40/60 to 60/40.
TIMING CHARACTERISTICS
1, 2
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7868 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+0.3 V
V
OUT
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
to V
DD
V
IN
to AGND . . . . . . . . . . . . . . . . V
SS
–0.3 V to V
DD
+ 0.3 V
RO ADC to AGND . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
RO DAC to AGND . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
RI DAC to AGND . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Inputs to AGND . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Outputs to AGND . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
T Version . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
DIP
RO ADC
DGND
TCLK
DT
RI DAC
AGND
CONTROL
CLK
RCLK
DR
DGND
AGND
RO DAC
NC
V
DD
NC = NO CONNECT
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
10
11
12
9
AD7868
TOP VIEW
(Not to Scale)
CONVST
RFS
V
SS
V
OUT
V
IN
TFS
LDAC
V
DD
V
SS
SOIC
RO ADC
DGND
TCLK
DT
RI DAC
AGND
CONTROL
CLK
RCLK
DR
DGND
AGND
RO DAC
NC
V
DD
NC = NO CONNECT
1
7
8
9
24
23
22
21
20
19
18
17
16
15
14
12
13
AD7868
TOP VIEW
(Not to Scale)
CONVST
RFS
V
SS
V
OUT
V
IN
TFS
LDAC
10
11
3
4
5
6
2
28
27
26
25
NC
NC
NC
NC
V
DD
V
SS
PIN CONFIGURATIONS
(V
DD
= +5 V 6 5%, V
SS
= –5 V 6 5%, AGND = DGND = 0 V)
