TISP9110MDMR-S

APRIL 2013 - REVISED NOVEMBER 2013
Specifi cations are subject to change without notice.
The device characteristics and parameters in this data sheet can and do vary in different applications and actual device performance may vary over time.
Users should verify actual device performance in their specifi c applications.
TISP9110MDM Overvoltage Protector
TISP9110MDM
INTEGRATED COMPLEMENTARY BUFFERED-GATE SCRS
FOR DUAL POLARITY SLIC OVERVOLTAGE PROTECTION
Device Symbol
High Performance Protection for SLICs with +ve and -ve
Battery Supplies
– Wide -110 V to +110 V Programming Range
– Low 5 mA max. Gate Triggering Current
– Dynamic Protection Performance Specifi ed for
International Surge Waveshapes
Applications include:
– Wireless Local Loop
– Access Equipment
– Regenerated POTS
– VOIP Applications
Rated for International Surge Wave Shapes
How To Order
8-SOIC (210 mil) Package (Top View)
Description
The Model TISP9110MDM is a programmable overvoltage
protection device designed to protect modern dual polarity supply
rail ringing SLICs (Subscriber Line Interface Circuits) against
overvoltages on the telephone line. Overvoltages can be caused
by lightning, a.c. power contact and induction. Four separate
protection structures are used; two positive and two negative
to provide optimum protection during Metallic (Differential) and
Longitudinal (Common Mode) protection conditions in both polar-
ities. Dynamic protection performance is specifi ed under typical
international surge waveforms from Telcordia GR-1089-CORE,
ITU-T K.44 and YD/T 950.
Wave Shape Standard
I
PPSM
A
2/10 GR-1089-CORE 150
10/700 ITU-T K.20/21/45 80
10/1000 GR-1089-CORE 50
MD-8SOIC(210)-003-a
NC - No internal connection
Terminal typical application names shown in
parenthesis
1
2
3
45
6
7
8
NC
Ground
Ground
NC
(-V
(BAT)
) G1
(Tip or Ring) Line
(Ring or Tip) Line
(+V
(BAT)
) G2
SD-TISP9-001-
a
G2
G1
Ground
Line
Line
The Model TISP9110MDM is programmed by connecting the G1
and G2 gate terminals to the negative (-V
(BAT)
) and positive (+V
(BAT)
) SLIC Battery supplies respectively. This creates a protector operating at
typically +1.4 V above +V
(BAT)
and -1.4 V below -V
(BAT)
under a.c. power induction and power contact conditions. The protector gate circuitry
incorporates 4 separate buffer transistors designed to provide independent control for each protection element. The gate buffer transistors
minimize supply regulation issues by reducing the gate current drawn to around 5 mA, while the high voltage base emitter structures eliminate
the need for expensive reverse bias protection gate diodes.
The Model TISP9110MDM is rated for common surges contained in regulatory requirements such as ITU-T K.20, K.45, Telcordia GR-1089-
CORE, YD/T 950. With the use of appropriate overcurrent protection devices such as the Bourns
®
Multifuse
®
and Telefuse
devices, circuits
can be designed to comply with modern telecom standards.
*RoHS Directive 2002/95/EC Jan. 27, 2003 including annex and RoHS Recast 2011/65/EU June 8, 2011.
Device Package Carrier Marking Code Standard Quantity
TISP9110MDM 8-SOIC (210 mil) Embossed Tape Reeled TISP9110MDMR-S 9110M 2000
Order As
*RoHS COM
PLIANT
APRIL 2013 - REVISED NOVEMBER 2013
Specifi cations are subject to change without notice.
The device characteristics and parameters in this data sheet can and do vary in different applications and actual device performance may vary over time.
Users should verify actual device performance in their specifi c applications.
Absolute Maximum Ratings, T
A
= 25 °C (Unless Otherwise Noted)
TISP9110MDM Overvoltage Protector
Electrical Characteristics for any Section, T
A
= 25 °C (Unless Otherwise Noted)
Parameter Test Conditions Min Typ Max Unit
I
D
Off-state current
V
D
= V
DRM
, V
G1(Line)
= 0, V
G2
≥ +5 V
V
D
= V
DRM
, V
G2(Line)
= 0, V
G1
≥ -5 V
T
A
= 25 °C
T
A
= 85 °C
T
A
= 25 °C
T
A
= 85 °C
-5
-50
+5
+50
μA
I
G1(Line)
Negative-gate leakage current V
G1(Line)
= -220 V - 5 μA
I
G2(Line)
Positive-gate leakage current V
G2(Line)
= +220 V + 5 μA
V
G1L(BO)
Gate - Line impuls e breakover voltage
V
G1
= -100 V, I
T
= -100 A (see Note 6)
V
G1
= -100 V, I
T
= -30 A
2/10 μs
10/1000 μs
-15
-11
V
V
G2L(BO)
Gate - Line impuls e breakover voltage
V
G2
= +100 V, I
T
= +100 A (see Note 6)
V
G2
= +100 V, I
T
= +30 A
2/10 μs
10/1000 μs
+15
+11
V
I
H
- Negative holding current V
G1
= -60 V, I
T
= -1 A, di/dt = 1 A/ms -150 mA
I
G1T
Negative-gate trigger current I
T
=-5A, t
p(g)
≥2s, V
G1
= -60 V + 5 mA
I
G2T
Positive-gate trigger current I
T
=5A, t
p(g)
≥2s, V
G2
= 60 V - 5 mA
C
O
Line - Ground off-state capacitance f = 1 MHz, V
D
= -3 V, G1 & G2 open circuit 33 pF
NOTE: 6. Voltage measurements should be made with an oscillosc ope with limited bandw idth (20 MHz) to avoid high frequency noise.
Rating Symbol Value Unit
Repetitive peak off-state voltage
V
G1(Line)
=0, V
G2
+5 V
V
G2(Line)
=0, V
G1
≥-5 V
V
DRM
-120
+120
V
Non-repetitive peak impulse current (see Notes 1, 2, 3 and 4)
I
PPSM
±150
±80
±50
A
2/10 μs (Telcordia GR-1089-CORE)
5/310 μs (ITU-T K.20, K.21 & K.45, K.44 open-circuit voltage wave shape 10/700 ms)
10/1000 μs (T elcordia GR-1089-CORE)
Non-repetitive peak on-state current, 50 Hz / 60 Hz (see Notes 1, 2, 3 and 5)
I
TSM
9.0
5.0
1.7
A
0.2 s
1 s
900 s
Maximum negative battery supply voltage V
G1M
-110 V
Maximum positive battery supply voltage V
G2M
+110 V
Maximum differential battery supply voltage
V
(BAT)M
220 V
Junction temperature T
J
-40 to +150 °C
Storage temperature range T
stg
-65 to +150 °C
NOTES: 1. Initially the device must be in thermal equilibrium with T
J
= 25 °C. The surge may be repeated after the device returns to its initial
conditions.
2. The rated current values may be applied to either of the Line to Ground terminal pairs. Additionally, both terminal pairs may have
their rated current values applied simultaneously (in this case the Ground terminal current will be twice the rated current value of a
single terminal pair).
3. Rated currents only apply if pins 6 & 7 (Ground) are connected together.
4. Applies for the following bias conditions: V
G1
= -20 V to -110 V, V
G2
= 0 V to +110 V.
5. EIA/JESD51-2 environment and EIA/JESD51-7 high effective thermal conductivity test board (multi-layer) connected with 0.6 mm
printed wiring track widths.
APRIL 2013 - REVISED NOVEMBER 2013
Specifi cations are subject to change without notice.
The device characteristics and parameters in this data sheet can and do vary in different applications and actual device performance may vary over time.
Users should verify actual device performance in their specifi c applications.
Thermal Characteristics, T
A
= 25 °C (Unless Otherwise Noted)
Parameter Measurement Information
TISP9110MDM Overvoltage Protector
Parameter Test Conditions Min Typ Max Unit
R
θJA
Junction to ambient thermal resistance
EIA/JESD51-7 PCB, EIA/JESD51-2 Environment, P
TOT
= 4 W
(See Note 7)
55 °C/W
NOTE 7. EIA/JESD51-7 high effective thermal conductivity test board (multi-layer) connected with 0.6 mm printed wiring track widths.
Figure 1. Voltage-Current Characteristic
Unless Otherwise Noted, All Voltages are Referenced to the Ground Terminal
Quadrant III
Switching
Characteristic
-v
V
G1
V
D
I
H
I
TRM
I
PPSM
V
(BO)
+i
-i
I
D
PM-TISP9-001-a
I
TSM
V
G2
V
D
V
(BO)
I
H
I
TRM
I
PPSM
Quadrant I
Switching
Characteristic
I
D
+v
I
TSM

TISP9110MDMR-S

Mfr. #:
Manufacturer:
Bourns
Description:
SCRs Dual Polarity SLIC 150/80/50A
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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