MC100EP29DTG

© Semiconductor Components Industries, LLC, 2014
April, 2014 − Rev. 9
1 Publication Order Number:
MC10EP29/D
MC10EP29, MC100EP29
3.3V / 5V ECL Dual
Differential Data and Clock
D Flip-Flop With Set and
Reset
Description
The MC10/100EP29 is a dual master−slave flip−flop. The device
features fully differential Data and Clock inputs as well as outputs.
The MC10/100EP29 is functionally equivalent to the
MC10/100EL29. Data enters the master latch when the clock is LOW
and transfers to the slave upon a positive transition on the clock input.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs
are left open the D input will pull down to V
EE
and the D input will
bias around V
CC
/2. The outputs will go to a defined state, however the
state will be random based on how the flip flop powers up.
Both flip flops feature asynchronous, overriding Set and Reset
inputs. Note that the Set and Reset inputs cannot both be HIGH
simultaneously.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
The 100 Series contains temperature compensation.
Features
Maximum Frequency > 3 GHz Typical
500 ps Typical Propagation Delays
PECL Mode Operating Range: V
CC
= 3.0 V to 5.5 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= −3.0 V to −5.5 V
Open Input Default State
Safety Clamp on Inputs
These are Pb−Free Devices
MARKING
DIAGRAM*
TSSOP−20
DT SUFFIX
CASE 948E
XXXX = MC10 or 100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
http://onsemi.com
(Note: Microdot may be in either location)
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
XXXX
EP29
ALYWG
G
1
20
QFN−20
MN SUFFIX
CASE 485E
XXXX
EP29
ALYWG
G
MC10EP29, MC100EP29
http://onsemi.com
2
V
BB
Figure 1. 20−Lead Pinout (Top View) and Logic Diagram
CLK0 D1CLK1
1718 16 15 14 13 12
435678
9
Q0
11
10
Q0S0 S1
V
CC
Q1 Q1 V
EE
D0
1920
21
R0V
CC
CLK0 D1D0 CLK1
R1
CLKD
SR
Q
Q
CLK D
RSQ
Q
Warning: All V
CC
and V
EE
pins must be externally connected
to Power Supply to guarantee proper operation.
1
2
3
4
5
15
14
13
12
11
678910
20 19 18 17 16
Figure 1. QFN−20 Pinout (Top View)
S0
Q0
Q0
D0 R0V
CC
Q1
Q1
R1
S1
V
EE
CLK0
CLK0
CLK1
D0
V
BB
CLK1
D1 D1
V
CC
Exposed Pad
NOTE: The Exposed Pad (EP) on package bottom must be attached to a heat−sinking conduit.
The Exposed Pad may only be electrically connected to V
EE
.
MC10/100EP29
Table 1. PIN DESCRIPTION
Pin Function
D0*, D0*; D1*, D1* ECL Differential Data Inputs
R0*, R1* ECL Reset Inputs
CLK0*, CLK0* ECL Differential Clock Inputs
CLK1*, CLK1* ECL Differential Clock Inputs
S0* S1* ECL Set Inputs
Q0, Q0; Q1, Q1 ECL Differential Data Outputs
V
BB
Reference Voltage Output
V
CC
Positive Supply
V
EE
Negative Supply
EP Exposed Pad
*Pins will default LOW when left open.
Table 2. TRUTH TABLE
R S D CLK Q Q
L L L Z L H
L L H Z H L
H L X X L H
L H X X H L
H H X X Undef Undef
Z = LOW to HIGH Transition
X = Don’t Care
MC10EP29, MC100EP29
http://onsemi.com
3
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor N/A
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg
TSSOP−20
QFN−20
Level 1
N/A
Level 3
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 383 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
PECL Mode Power Supply V
EE
= 0 V 6 V
V
EE
NECL Mode Power Supply V
CC
= 0 V −6 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
v V
CC
V
I
w V
EE
6
−6
V
V
I
out
Output Current Continuous
Surge
50
100
mA
mA
I
BB
V
BB
Sink/Source ± 0.5 mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
20 TSSOP
20 TSSOP
140
100
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case) Standard Board 20 TSSOP 23 to 41 °C/W
q
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
QFN−20
QFN−20
47
33
°C/W
°C/W
q
JC
Thermal Resistance (Junction−to−Case) Standard Board QFN−20 18 °C/W
T
sol
Wave Solder Pb
Pb−Free
265
265
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.

MC100EP29DTG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Flip Flops 3.3V/5V ECL Dual Diff Data D-Type
Lifecycle:
New from this manufacturer.
Delivery:
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