LTC2444/LTC2445/
LTC2448/LTC2449
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Table 6. LTC2444/LTC2445/LTC2448/LTC2449 Interface Timing Modes
CONFIGURATION
SCK
SOURCE
CONVERSION
CYCLE
CONTROL
DATA
OUTPUT
CONTROL
CONNECTION
AND
WAVEFORMS
External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 5, 6
External SCK, 2-Wire I/O External SCK SCK Figure 7
Internal SCK, Single Cycle Conversion Internal
CS CS
Figures 8, 9
Internal SCK, 2-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 10
applicaTions inForMaTion
Speed Multiplier Mode
In addition to selecting the speed/resolution, a speed
multiplier mode is used to double the output rate while
maintaining the selected resolution. The last bit of the
5-bit speed/resolution control word (TWOX, see Table 5)
determines if the output rate is 1X (no speed increase) or
2X (double the selected speed).
While operating in the 1X mode, the device combines two
internal conversions for each conversion result in order
to remove the ADC offset. Every conversion cycle, the
offset and offset drift are transparently calibrated greatly
simplifying the user interface. The resulting conversion
result has no latency. The first conversion following a
newly selected speed/resolution and input channel is
valid. This is identical to the operation of the LTC2440,
LTC2414 and LTC2418.
While operating in the 2X mode, the device performs a
running average of the last two conversion results. This
automatically removes the offset and drift of the device
while increasing the output rate by 2X. The resolution
(noise) remains the same. If a new channel is selected,
the conversion result is valid for all conversions after
the first conversion (one cycle latency). If a new speed/
resolution is selected, the first conversion result is valid
but the resolution (noise) is a function of the running av-
erage. All subsequent conversion results are valid. If the
mode is changed from either 1X to 2X or 2X to 1X without
changing the resolution or channel, the first conversion
result is valid.
If an external buffer/amplifier circuit is used for the
LTC2445/LTC2449, the 2X mode can be used to increase
the settling time of the amplifier between readings. While
operating in the 2X mode, the multiplexer output (input
to the external buffer/amplifier) is switched at the end of
each conversion cycle. Prior to concluding the data out/
in cycle, the analog multiplexer output is switched. This
occurs at the end of the conversion cycle (just prior to
the data output cycle) for auto calibration. The time re
-
quired to read the conversion enables more settling time
for the external buffer/amplifier. The offset/offset drift of
the external amplifier is automatically removed by the
converter’s auto calibration sequence for both the 1X and
2X speed modes.
While operating in the 1X mode, if a new input channel
is selected the multiplexer is switched on the falling edge
of the 14th SCK (once the complete data input word is
programmed). The remaining data output sequence time
can be used to allow the external buffer/amplifier to settle.
BUSY
The BUSY output (Pin 2) is used to monitor the state of
conversion, data output and sleep cycle. While the part is
converting, the BUSY pin is HIGH. Once the conversion is
complete, BUSY goes LOW indicating the conversion is
complete and data out is ready. The part now enters the
LOW power sleep state. BUSY remains LOW while data is
shifted out of the device and SDI is shifted into the device. It
goes HIGH at the conclusion of the data input/output cycle
indicating a new conversion has begun. This rising edge
may be used to flag the completion of the data read cycle.
Serial Interface Timing Modes
The LTC2444/LTC2445/LTC2448/LTC2449’s 3- or 4-wire
interface is SPI and MICROWIRE compatible. This interface
offers several flexible modes of operation. These include
internal/external serial clock, 3- or 4-wire I/O, single cycle
conversion and autostart. The following sections describe
each of these serial interface timing modes in detail. In all
these cases, the converter can use the internal oscillator
(F
O
= LOW) or an external oscillator connected to the F
O
pin. Refer to Table6 for a summary.
LTC2444/LTC2445/
LTC2448/LTC2449
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applicaTions inForMaTion
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 0
LSB
Hi-Z
2444589 F05
SIG
BIT 29
“0”
BIT 30
EOC
Hi-Z
CS
SCK
(EXTERNAL)
SDI
SDO
BUSY
BIT 31
1 0 EN SGL A2 A1 A0 OSR3 OSR2 OSR1 OSR0 TWOXODD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 32
CONVERSION SLEEP DATA OUTPUT
CONVERSION
TEST EOC TEST EOC
V
CC
F
O
REF
+
REF
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28 35
29
30
8
15
16
23
7
38
37
1,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUTS
2
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1µF
4.5V TO 5.5V
LTC2448
4-WIRE
SPI INTERFACE
BUSY
Figure 5. External Serial Clock, Single Cycle Operation
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift
out the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.
The serial clock mode is selected by the EXT
pin. To select
the external serial clock mode, EXT must be tied low.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC=1 (BUSY = 1) while a conversion is in progress
and EOC = 0 (BUSY = 0) if the device is in the sleep state.
Independent of CS, the device automatically enters the
low power sleep state once the conversion is complete.
When the device is in the sleep state (
EOC
= 0), its con-
version result is held in an internal static shift register.
The device remains in the sleep state until the first rising
edge of SCK is seen. Data is
shifted out the SDO pin on
each falling edge of SCK. This enables external circuitry
to latch the output on the rising edge of SCK.
EOC
can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. On the 32nd falling edge of SCK, the device
begins a new conversion. SDO goes HIGH (
EOC
= 1) and
BUSY goes HIGH indicating a conversion is in progress.
LTC2444/LTC2445/
LTC2448/LTC2449
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At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z
and BUSY monitored for the completion of a conversion.
As described above, CS may be pulled LOW at any time
in order to monitor the conversion status on the SDO pin.
Typically,
CS
remains LOW during the data output state.
However, the data output state may be aborted by pull-
ing
CS
HIGH anytime between the fifth falling edge and
the 32nd falling edge of SCK, see Figure 6. On the rising
edge of
CS
, the device aborts the data output state and
immediately initiates a new conversion.
Thirteen serial
input data bits are required in order to properly program
the speed/resolution and input channel. If the data output
sequence is aborted prior to the 13th rising edge of SCK,
the new input data is ignored, and the previously selected
speed/resolution and channel are used for the next conver-
sion cycle.
This is useful for systems not requiring all 32
bits of output data, aborting an invalid conversion cycle or
synchronizing the start of a conversion. If a new channel
is being programmed, the rising edge of
CS
must come
after the 14th falling edge of SCK in order to store the
data input sequence.
applicaTions inForMaTion
CS
SCK
(EXTERNAL)
SDI
SDO
BUSY
1 2 3 4 5 6 1 5
MSB
BIT 28 BIT 27 BIT 26 BIT 25
SIG
BIT 29
“0”
BIT 30
EOC
Hi-Z Hi-Z
BIT 31
2444589 F06
CONVERSION
SLEEP
SLEEP
DATA OUTPUT DATA OUTPUT
CONVERSION
CONVERSION
TEST EOC
DON'T CARE DON'T CARE
V
CC
F
O
REF
+
REF
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28 35
29
30
8
15
16
23
7
38
37
1,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUTS
2
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1µF
4.5V TO 5.5V
LTC2448
4-WIRE
SPI INTERFACE
BUSY
DON'T CARE
Figure 6. External Serial Clock, Reduced Output Data Length

LTC2449CUHF#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 24-Bit 8-ch. Diff., High Speed Delta-Sigma ADC
Lifecycle:
New from this manufacturer.
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