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ADCLK946BCPZ

P1-P3P4-P6P7-P9P10-P12P13-P13
ADCLK946
Rev. A | Page 3 of 12
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical (typ) values are given for V
CC
− V
EE
= 3.3 V and T
A
= 25°C, unless otherwise noted. Minimum (min) and maximum (max) values
are given over the full V
CC
− V
EE
= 3.3 V ± 10% and T
A
= −40°C to +85°C variation, unless otherwise noted.
Table 1. Clock Inputs and Outputs
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC INPUT CHARACTERISTICS
Input Voltage High Level V
IH
V
EE
+ 1.6 V
CC
V
Input Voltage Low Level V
IL
V
EE
V
CC
− 0.2 V
Input Differential Range V
ID
0.4 3.4 V p-p ±1.7 V between input pins
Input Capacitance C
IN
0.4 pF
Input Resistance
Single-Ended Mode 50 Ω
Differential Mode 100 Ω
Common Mode 50 kΩ Open V
T
Input Bias Current 20 µA
Hysteresis 10 mV
DC OUTPUT CHARACTERISTICS
Output Voltage High Level V
OH
V
CC
− 1.26 V
CC
− 0.76 V 50 Ω to (V
CC
− 2.0 V)
Output Voltage Low Level V
OL
V
CC
− 1.99 V
CC
− 1.54 V 50 Ω to (V
CC
− 2.0 V)
Output Voltage, Single-Ended V
O
610 960 mV V
OH
− V
OL
, output static
Reference Voltage V
REF
Output Voltage (V
CC
+ 1)/2 V −500 µA to +500 µA
Output Resistance 235 Ω
Table 2. Timing Characteristics
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
AC PERFORMANCE
Maximum Output Frequency 4.5 4.8 GHz
See Figure 4 for differential output voltage vs.
frequency, >0.8 V differential output swing
Output Rise/Fall Time t
R,
t
F
40 75 90 ps 20% to 80% measured differentially
Propagation Delay t
PD
150 185 220 ps V
ICM
= 2 V, V
ID
= 1.6 V p-p
Temperature Coefficient 50 fs/°C
Output-to-Output Skew 9 28 ps
Part-to-Part Skew
1
45 ps V
ID
= 1.6 V p-p
Additive Time Jitter
Integrated Random Jitter 28 fs rms BW = 12 kHz − 20 MHz, CLK = 1 GHz
Broadband Random Jitter
2
75 fs rms V
ID
= 1.6 V p-p, 8 V/ns, V
ICM
= 2 V
Crosstalk-Induced Jitter
3
90 fs rms
CLOCK OUTPUT PHASE NOISE
Absolute Phase Noise Input slew rate > 1 V/ns (see Figure 11 for more details)
f
IN
= 1 GHz −119 dBc/Hz @ 100 Hz offset
−134 dBc/Hz @ 1 kHz offset
−145 dBc/Hz @ 10 kHz offset
−150 dBc/Hz @ 100 kHz offset
−150 dBc/Hz >1 MHz offset
1
The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
2
Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method.
3
The amount of added jitter measured at the output while two related, asynchronous, differential frequencies are applied to the inputs.
ADCLK946
Rev. A | Page 4 of 12
Table 3. Power
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
Supply Voltage Requirement V
CC
− V
EE
2.97 3.63 V 3.3 V + 10%
Power Supply Current Static
Negative Supply Current I
VEE
90 115 mA V
CC
− V
EE
= 3.3 V ± 10%
Positive Supply Current I
VCC
245 275 mA V
CC
− V
EE
= 3.3 V ± 10%
Power Supply Rejection
1
PSR
VCC
<3 ps/V V
CC
− V
EE
= 3.3 V ± 10%
Output Swing Supply Rejection
2
PSR
VCC
28 dB V
CC
− V
EE
= 3.3 V ± 10%
1
Change in t
PD
per change in V
CC
.
2
Change in output swing per change in V
CC
.
ADCLK946
Rev. A | Page 5 of 12
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage
V
CC
− V
EE
6.0 V
Input Voltage
CLK, CLK V
EE
− 0.5 V to
V
CC
+ 0.5 V
CLK, CLK to V
T
Pin (CML, LVPECL
Termination)
±40 mA
CLK to CLK
±1.8 V
Input Termination, V
T
to CLK, CLK
±2 V
Maximum Voltage on Output Pins V
CC
+ 0.5 V
Maximum Output Current 35 mA
Voltage Reference (V
REF
) V
CC
to V
EE
Operating Temperature Range
Ambient −40°C to +85°C
Junction 150°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
DETERMINING JUNCTION TEMPERATURE
To determine the junction temperature on the application
printed circuit board (PCB), use the following equation:
T
J
= T
CASE
+ (Ψ
JT
× P
D
)
where:
T
J
is the junction temperature (°C).
T
CASE
is the case temperature (°C) measured by the customer at
the top center of the package.
Ψ
JT
is as indicated in Table 5.
P
D
is the power dissipation.
Values of θ
JA
are provided for package comparison and PCB
design considerations. θ
JA
can be used for a first-order approx-
imation of T
J
by the equation
T
J
= T
A
+ (
θ
JA
× P
D
)
where T
A
is the ambient temperature (°C).
Values of θ
JB
are provided in Table 5 for package comparison
and PCB design considerations.
ESD CAUTION
THERMAL PERFORMANCE
Table 5.
Parameter Symbol Description Value
1
Unit
Junction-to-Ambient Thermal Resistance
Still Air
0.0 m/sec Airflow
θ
JA
Per JEDEC JESD51-2 54.3 °C/W
Moving Air
1.0 m/sec Airflow
θ
JMA
Per JEDEC JESD51-6 47.5 °C/W
2.5 m/sec Airflow
θ
JMA
Per JEDEC JESD51-6 42.6 °C/W
Junction-to-Board Thermal Resistance
Moving Air
1.0 m/sec Airflow
θ
JB
Per JEDEC JESD51-8 (moving air) 33.0 °C/W
Junction-to-Case Thermal Resistance (Die-to-Heat Sink)
Moving Air
θ
JC
Per MIL-Std. 883, Method 1012.1 2.0 °C/W
Junction-to-Top-of-Package Characterization Parameter
Still Air
0 m/sec Airflow
Ψ
JT
Per JEDEC JESD51-2 0.9 °C/W
1
Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the
application to determine if they are similar to those assumed in these calculations.
P1-P3P4-P6P7-P9P10-P12P13-P13

ADCLK946BCPZ

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Buy ADCLK946BCPZ
Manufacturer:
Analog Devices Inc.
Description:
Clock Buffer 6 LVPECL Output SiGe
Lifecycle:
New from this manufacturer.
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