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ADCLK946BCPZ

P1-P3P4-P6P7-P9P10-P12P13-P13
ADCLK946
Rev. A | Page 6 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1V
EE
2CLK
3CLK
4V
REF
5V
T
6V
EE
15 Q3
16 Q2
17 Q2
18 V
CC
14 Q3
13 V
CC
7V
EE
8Q5
9Q5
11Q4
12V
EE
10Q4
21
Q1
22
Q0
23
Q0
24
V
CC
20
Q1
19
V
EE
ADCLK946
TOP VIEW
(Not to Scale)
NOTES:
1. EXPOSED PADDLE MUST BE CONNECTED TO V
EE
.
08053-002
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1, 6, 7, 12, 19 V
EE
Negative Supply Pin.
2 CLK Differential Input (Positive).
3
CLK
Differential Input (Negative).
4 V
REF
Reference Voltage. This pin provides the reference voltage for biasing ac-coupled CLK and CLK inputs.
5 V
T
Center Tap. This pin provides the center tap of a 100 Ω input resistor for CLK and CLK inputs.
8, 9
Q5, Q5
Differential LVPECL Outputs.
10, 11
Q4, Q4
Differential LVPECL Outputs.
13, 18, 24 V
CC
Positive Supply Pin.
14, 15
Q3, Q3
Differential LVPECL Outputs.
16, 17
Q2, Q2
Differential LVPECL Outputs.
20, 21
Q1, Q1
Differential LVPECL Outputs.
22, 23
Q0, Q0
Differential LVPECL Outputs.
EPAD EPAD must be soldered to V
EE
.
ADCLK946
Rev. A | Page 7 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
V
CC
= 3.3 V, V
EE
= 0.0 V, V
ICM
= V
REF
, T
A
= 25°C, clock outputs terminated at 50 Ω to V
CC
− 2 V, unless otherwise noted.
C3
C4
C3
100mV/DIV 500ps/DIV
08053-003
Figure 3. LVPECL Output Waveform @ 200 MHz
1.8
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
0 1000 2000 3000 4000 5000
DIFFERENTIAL OUTPUT VOLTAGE (V)
FREQUENCY (MHz)
08053-004
Figure 4. Differential Output Swing vs. Frequency
205
160
165
170
175
180
185
190
195
200
0 1.81.61.41.21.00.80.60.40.2
PROPAGATION DELAY (ps)
DIFFERENTIAL INPUT VOLTAGE SWING (V)
08053-005
Figure 5. Propagation Delay vs. Differential Input Voltage
C4
C3
C4
100mV/DIV 100ps/DIV
08053-006
Figure 6. LVPECL Output Waveform @ 1000 MHz
Figure 7. Propagation Delay vs. Temperature
205
165
175
185
195
0.9 3.12.92.72.52.32.11.91.71.51.31.1
PROPAGATION DELAY (ps)
DC COMMON-MODE VOLTAGE (V)
+85°C
+25°C
–40°C
08053-008
Figure 8. Propagation Delay vs. Common-Mode Voltage vs. Temperature,
Input Slew Rate > 25 V/ns
ADCLK946
Rev. A | Page 8 of 12
1.56
1.54
1.52
1.50
1.48
1.46
1.44
1.42
2.75 2.85 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 3.75
DIFFERENTIAL OUTPUT VOLTAGE SWING (V)
POWER SUPPLY (V)
+85°C
+25°C
–40°C
08053-009
Figure 9. Differential Output Swing vs. Power Supply Voltage vs. Temperature,
V
ID
= 1.6 V p-p
300
250
200
150
100
50
0
3.633.302.97
CURRENT (mA)
POWER SUPPLY (V)
I
VCC
I
VEE
+85°C
+25°C
–40°C
08053-010
Figure 10. Power Supply Current vs. Power Supply Voltage vs. Temperature,
All Outputs Loaded (50 Ω to V
CC
− 2 V)
–90
–170
–160
–150
–140
–130
–120
–110
–100
10 100 1k 10k 100k 1M 10M 100M
PHASE NOISE (dBc/Hz)
FREQUENCY OFFSET (Hz)
CLOCK SOURCE
ADCLK946
08053-011
Figure 11. Absolute Phase Noise Measured @1 GHz with Agilent E5052
300
250
200
150
100
50
0
0 252015105
RANDOM JITTER (
f
S
rms)
INPUT SLEW RATE (V/ns)
08053-012
Figure 12. RMS Jitter vs. Input Slew Rate, V
ID
Method
P1-P3P4-P6P7-P9P10-P12P13-P13

ADCLK946BCPZ

Mfr. #:
Buy ADCLK946BCPZ
Manufacturer:
Analog Devices Inc.
Description:
Clock Buffer 6 LVPECL Output SiGe
Lifecycle:
New from this manufacturer.
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