10–2 Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
Table 10–3. HardCopy APEX Device DC Operating Conditions (Part 1 of 2) Notes (6), (7), (8)
Symbol Parameter Conditions Min Typ Max Unit
V
IH
High-level LVTTL, CMOS, or
3.3-V PCI input voltage
1.7,
0.5 × V
CCIO
(8)
4.1 V
V
IL
Low-level LVTTL, CMOS, or
3.3-V PCI input voltage
–0.5 0.8,
0.3 × V
CCIO
(8)
V
V
OH
3.3-V high-level LVTTL output
voltage
I
OH
= –12 mA DC,
V
CCIO
= 3.00 V (9)
2.4 V
3.3-V high-level LVCMOS
output voltage
I
OH
= –0.1 mA DC,
V
CCIO
= 3.00 V (9)
V
CCIO
–0.2 V
3.3-V high-level PCI output
voltage
I
OH
= –0.5 mA DC,
V
CCIO
= 3.00 to 3.60 V
(9)
0.9 × V
CCIO
V
2.5-V high-level output
voltage
I
OH
= –0.1 mA DC,
V
CCIO
= 2.30 V (9)
2.1 V
I
OH
= –1 mA DC,
V
CCIO
= 2.30 V (9)
2.0 V
I
OH
= –2 mA DC,
V
CCIO
= 2.30 V (9)
1.7 V
V
OL
3.3-V low-level LVTTL output
voltage
I
OL
= 12 mA DC,
V
CCIO
= 3.00 V (10)
0.4 V
3.3-V low-level LVCMOS
output voltage
I
OL
= 0.1 mA DC,
V
CCIO
= 3.00 V (10)
0.2 V
3.3-V low-level PCI output
voltage
I
OL
= 1.5 mA DC,
V
CCIO
= 3.00 to 3.60 V
(10)
0.1 × V
CCIO
V
2.5-V low-level output voltage I
OL
= 0.1 mA DC,
V
CCIO
= 2.30 V (10)
0.2 V
I
OL
= 1 mA DC,
V
CCIO
= 2.30 V (10)
0.4 V
I
OL
= 2 mA DC,
V
CCIO
= 2.30 V (10)
0.7 V
I
I
Input pin leakage current (11) V
I
= 4.1 to –0.5 V –10 10 μA
I
OZ
Tri-stated I/O pin leakage
current (11)
V
O
= 4.1 to 0.5 V –10 10 μA
I
CC0
V
CC
supply current (standby)
(All ESBs in power-down
mode)
V
I
= ground, no load,
no toggling inputs,
-7 speed grade
10 mA
V
I
= ground, no load,
no toggling inputs,
-8, -9 speed grades
5mA
Altera Corporation 10–3
September 2008
Recommended Operating Conditions
R
CONF
Value of I/O pin pull-up
resistor before and during
configuration emulation
V
CCIO
=3.0 V (12) 20 50 kΩ
V
CCIO
= 2.375 V (12) 30 80 kΩ
V
CCIO
= 1.71 V (12) 60 150 kΩ
Table 10–4. HardCopy APEX Device Capacitance Note (13)
Symbol Parameter Conditions Min Typ Max
C
IN
Input capacitance V
IN
= 0 V, f = 1.0 MHz 8 pF
C
INCLK
Input capacitance on
dedicated clock pin
V
IN
= 0 V, f = 1.0 MHz 12 pF
C
OUT
Output capacitance V
OUT
= 0 V, f = 1.0 MHz 8 pF
Notes to Tab le 1 0– 1 through 10–4:
(1) Refer to the Operating Requirements for Altera Devices Data Sheet.
(2) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to0.5 V or overshoot to 4.6 V for
input currents less than 100 mA and periods shorter than 20 ns.
(3) Numbers in parentheses are for industrial-temperature-range devices.
(4) Maximum V
CC
rise time is 100 ms, and V
CC
must rise monotonically.
(5) All pins (including dedicated inputs, clock, I/O, and JTAG pins) may be driven before V
CCINT
and V
CCIO
are
powered.
(6) Typical values are for T
A
= 25° C, V
CCINT
= 1.8 V, and V
CCIO
= 1.8 V, 2.5 V, or 3.3 V.
(7) These values are specified under the HardCopy device recommended operating conditions, as shown in Table 10–2
on page 10–1.
(8) Refer to AN 117: Using Selectable I/O Standards in Altera Devices for the V
IH
, V
IL
, V
OH
, V
OL
, and I
I
parameters when
V
CCIO
= 1.8 V.
(9) The APEX 20KE input buffers are compatible with 1.8-V, 2.5-V and 3.3-V (LVTTL and LVCMOS) signals.
Additionally, the input buffers are 3.3-V PCI compliant. Input buffers also meet specifications for GTL+, CTT, AGP,
SSTL-2, SSTL-3, and HSTL.
(10) The I
OH
parameter refers to high-level TTL, PCI, or CMOS output current.
(11) This value is specified for normal device operation. The value may vary during power-up.
(12) Pin pull-up resistance values will be lower if an external source drives the pin higher than V
CCIO
.
(13) Capacitance is sample-tested only.
Table 10–3. HardCopy APEX Device DC Operating Conditions (Part 2 of 2) Notes (6), (7), (8)
Symbol Parameter Conditions Min Typ Max Unit
10–4 Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
Tables 10–5 through 10–20 list the DC operating specifications for the
supported I/O standards. These tables list minimal specifications only;
HardCopy devices may exceed these specifications.
Table 10–5. LVTTL I/O Specifications
Symbol Parameter Conditions Minimum Maximum Units
V
CCIO
Output supply
voltage
3.0 3.6 V
V
IH
High-level input
voltage
2.0 V
CCIO
+ 0.3 V
V
IL
Low-level input
voltage
–0.3 0.8 V
I
I
Input pin leakage
current
V
IN
= 0 V or 3.3 V –10 10 μA
V
OH
High-level output
voltage
I
OH
= –12 mA,
V
CCIO
= 3.0 V (1)
2.4 V
V
OL
Low-level output
voltage
I
OL
= 12 mA,
V
CCIO
= 3.0 V (2)
0.4 V
Table 10–6. LVCMOS I/O Specifications
Symbol Parameter Conditions Minimum Maximum Units
V
CCIO
Power supply
voltage range
3.0 3.6 V
V
IH
High-level input
voltage
2.0 V
CCIO
+ 0.3 V
V
IL
Low-level input
voltage
–0.3 0.8 V
I
I
Input pin leakage
current
V
IN
= 0 V or 3.3 V –10 10 μA
V
OH
High-level output
voltage
V
CCIO
= 3.0 V
I
OH
= –0.1 mA (1)
V
CCIO
– 0.2 V
V
OL
Low-level output
voltage
V
CCIO
= 3.0 V
I
OL
= 0.1 mA (2)
0.2 V

HC20K600BC652AD

Mfr. #:
Manufacturer:
Intel
Description:
IC FPGA APEX 652BGA APEX HardCopy
Lifecycle:
New from this manufacturer.
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