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IDT72V3682L10PFG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
1
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4679/6
©
FEBRUARY 2009
3.3 VOLT CMOS SyncBiFIFO
TM
16,384 x 36 x 2
32,768 x 36 x 2
65,536 x 36 x 2
IDT72V3682
IDT72V3692
IDT72V36102
COMMERCIAL TEMPERATURE RANGE
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
FEATURES
••
••
• Memory storage capacity:
IDT72V3682 – 16,384 x 36 x 2
IDT72V3692 – 32,768 x 36 x 2
IDT72V36102 – 65,536 x 36 x 2
••
••
•
Supports clock frequencies up to 100MHz
••
••
•
Fast access times of 6.5ns
••
••
•
Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
••
••
• Two independent clocked FIFOs buffering data in opposite direc-
tions
••
••
• Mailbox bypass register for each FIFO
••
••
• Programmable Almost-Full and Almost-Empty flags
••
••
•
Microprocessor Interface Control Logic
••
••
•
FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA
••
••
•
FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB
••
••
•
Select IDT Standard timing (using EFA, EFB, FFA and FFB flags
functions) or First Word Fall Through timing (using ORA, ORB, IRA
and IRB flag functions)
••
••
•
Available in space-saving 120-pin Thin Quad Flatpack (TQFP)
••
••
•
Pin compatible to the lower density parts, IDT72V3622/72V3632/
72V3642/72V3652/72V3662/72V3672
••
••
•
Industrial temperature range (–40
°°
°°
°C to +85
°°
°°
°C) is available
••
••
•
Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
Mail 1
Register
Programmable Flag
Offset Registers
Input
Register
Output
Register
RAM
ARRAY
16,384 x 36
32,768 x 36
65,536 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
Input
Register
Output
Register
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
RST1
Mail 2
Register
MBF2
CLKB
CSB
W/RB
ENB
MBB
Port-B
Control
Logic
FIFO2,
Mail2
Reset
Logic
RST2
MBF1
FIFO 1
FIFO 2
16
EFB/ORB
AEB
36
36
FFB/IRB
AFB
B
0
- B
35
FFA/IRA
AFA
FS
0
FS
1
A
0
- A
35
EFA/ORA
AEA
4679 drw 01
36
36
Timing
Mode
FWFT
RAM
ARRAY
16,384 x 36
32,768 x 36
65,536 x 36
2
COMMERCIAL TEMPERATURE RANGE
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO
TM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
TQFP (PN120-1, order code: PF)
TOP VIEW
4679 drw 03
A
35
A
34
A
33
A
32
V
CC
A
31
A
30
GND
A
29
A
28
A
27
A
26
A
25
A
24
A
23
FWFT
A
22
V
CC
A
21
A
20
A
19
A
18
GND
A
17
A
16
A
15
A
14
A
13
V
CC
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B
35
B
34
B
33
B
32
GND
B
31
B
30
B
29
B
28
B
27
B
26
V
CC
B
25
B
24
GND
B
23
B
22
B
21
B
20
B
19
B
18
GND
B
17
B
16
V
CC
B
15
B
14
B
13
B
12
GND
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
91
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
V
CC
GND
CLKA
ENA
W/RA
CSA
FFA/IRA
EFA/ORA
V
CC
AFA
AEA
MBF2
MBA
RST1
FS0
GND
FS1
RST2
MBB
MBF1
V
CC
AEB
AFB
EFB/ORB
FFB/IRB
GND
CSB
W/RB
ENB
CLKB
GND
A
11
A
10
A
9
A
8
A
7
A
6
GND
A
5
A
4
A
3
V
CC
A
2
A
1
A
0
GND
B
0
B
1
B
2
B
3
B
4
B
5
GND
B
6
V
CC
B
7
B
8
B
9
B
10
B
11
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
DESCRIPTION
The IDT72V3682/72V3692/72V36102 are designed to run off a 3.3V
supply for exceptionally low-power consumption. These devices are mono-
lithic, high-speed, low-power, CMOS Bidirectional SyncFIFO (clocked) memo-
ries which support clock frequencies up to 100MHz and have read access times
as fast as 6.5ns. Two independent 16,384/32,768/65,536 x 36 dual-port
SRAM FIFOs on board each chip buffer data in opposite directions. Commu-
nication between each port may bypass the FIFOs via two 36-bit mailbox
registers. Each mailbox register has a flag to signal when new mail has been
stored.
These devices are a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
These devices have two modes of operation: In the IDT Standard mode,
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residing in memory). In the First Word Fall Through mode (FWFT), the first
long-word (36-bit wide) written to an empty FIFO appears automatically on the
outputs, no read operation required (Nevertheless, accessing subsequent
words does necessitate a formal read request). The state of the FWFT pin
during FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and EFB/
PIN CONFIGURATION
3
COMMERCIAL TEMPERATURE RANGE
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO
TM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/IRB). The
EF and FF functions are selected in the IDT Standard mode. EF indicates
whether or not the FIFO memory is empty. FF shows whether the memory is
full or not. The IR and OR functions are selected in the First Word Fall Through
mode. IR indicates whether or not the FIFO has available memory locations.
OR shows whether the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
Each FIFO has a programmable Almost-Empty flag (AEA and AEB) and a
programmable Almost-Full flag (AFA and AFB). AEA and AEB indicate when
a selected number of words remain in the FIFO memory. AFA and AFB indicate
when the FIFO contains more than a selected number of words.
FFA/IRA, FFB/IRB, AFA and AFB are two-stage synchronized to the port
clock that writes data into its array. EFA/ORA, EFB/ORB, AEA and AEB are two-
stage synchronized to the port clock that reads data from its array. Program-
mable offsets for AEA, AEB, AFA and AFB are loaded by using Port A. Three
default offset settings are also provided. The AEA and AEB threshold can be
set at 8, 16 or 64 locations from the empty boundary and the AFA and AFB
threshold can be set at 8, 16 or 64 locations from the full boundary. All these
choices are made using the FS0 and FS1 inputs during Reset.
Two or more devices may be used in parallel to create wider data paths. If,
at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption (I
CC) is at a minimum. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
The IDT72V3682/72V3692/72V36102 are characterized for operation
from 0°C to 70°C. Industrial temperature range (-40°C to +85°C) is available
by special order. They are fabricated using IDT’s high speed, submicron
CMOS technology.
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IDT72V3682L10PFG

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IC FIFO 32768X36 10NS 120QFP
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