16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
NOTE:
1.Read From FIFO1.
Figure 6. Port B Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
Figure 7. Port A Read Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
NOTE:
1.Read From FIFO2.
4679 drw 09
CLKB
EFB/ORB
ENB
MBB
CSB
W/RB
tCLK
tCLKH
tCLKL
tA
tMDV
tEN
tA
tENHtENH
Previous Data
W1
W2
(1)(1)
tENH
tDIS
No Operation
HIGH
tA
tMDV
tEN
tA
W1
W2
W3
(1)(1)(1)
tDIS
B0-B35
(FWFT Mode)
B0-B35
(IDT Standard Mode)
OR
tENS2
tENS2
tENS2
CLKA
EFA/ORA
ENA
MBA
CSA
W/RA
tCLK
tCLKHtCLKL
tENH
tENH
tENH
No Operation
tA
tEN
tA
W1
W2W3
(1)
(1)
(1)
tDIS
A0-A35
(FWFT Mode)
tEN
W2
(1)
(1)
tDIS
W1Previous Data
A0-A35
(Standard Mode)
tMDV
tAOR
tA
tMDV
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HIGH
tENS2
tENS2
tENS2
17
COMMERCIAL TEMPERATURE RANGE
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO
TM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
NOTE:
1.tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
Figure 8. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
CSA
WRA
MBA
IRA
A0 - A35
CLKB
ORB
CSB
W/RB
MBB
ENA
ENB
B0 -B35
CLKA
4679 drw 11
12
3
t
CLKH
t
CLKL
t
CLK
t
ENS2
t
ENS2
t
ENH
t
ENH
t
DS
t
DH
t
SKEW1
t
CLK
t
CLKL
t
POR
t
POR
t
ENS2
t
ENH
t
A
Old Data in FIFO1 Output RegisterW1
FIFO1Empty
LOW
HIGH
LOW
HIGH
LOW
t
CLKH
W1
HIGH
(1)
18
COMMERCIAL TEMPERATURE RANGE
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO
TM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
NOTE:
1.tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Figure 9.
EFBEFB
EFBEFB
EFB
Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)
