1
60V, 1A/2A Peak, Half Bridge Driver with 4V UVLO
HIP2103, HIP2104
The HIP2103 and HIP2104 are half bridge drivers designed for
applications using DC motors, three-phase brushless DC
motors, or other similar loads.
Two inputs (HI and LI) are provided to independently control
the high side driver (HO) and the low side driver (LO).
Furthermore, the two inputs can be configured to
enable/disable the device, thus lowering the number of
connections to a microcontroller and lowering costs.
The very low IDD bias current in the Sleep Mode prevents
battery drain when the device is not in use, thus eliminating
the need for an external switch to disconnect the driver from
the battery.
A fail-safe mechanism is included to improve system reliability
and to minimize the possibility of catastrophic bridge failures
due to controller malfunction. Internal logic prevents both
outputs from turning on simultaneously when HI and LI are
both high simultaneously. Dead-time is still required on the
rising edge of the HI (or LI) input when the LI (or HI) input
transitions low.
Integrated pull-down resistors on all of the inputs (LI, HI, VDen
and VCen) reduces the need for external resistors. An active
low resistance pull-down on the LO output ensures that the low
side bridge FET remains off during the Sleep Mode or when
VDD is below the undervoltage lockout (UVLO) threshold.
The HIP2104 has a 12V linear regulator and a 3.3V linear
regulator with separate enable pins. The 12V regulator
provides internal bias for VDD and the 3.3V regulator provides
bias for an external microcontroller (and/or other low voltage
ICs), thus eliminating the need for discrete LDOs or DC/DC
converters.
The HIP2103 is available in a 3x3mm, 8 Ld TDFN package and
the HIP2104 is available in a 4x4mm, 12 Ld DFN package.
Features
60V maximum bootstrap supply voltage
3.3V and 12V LDOs with dedicated enable pins (HIP2104)
5µA sleep mode quiescent current
4V undervoltage lockout
3.3V or 5V CMOS compatible inputs with hysteresis
Integrated bootstrap FET (replaces traditional boot strap diode)
Applications
Half bridge, full bridge and BLDC motor drives
(see Figures 21, 22, 23)
•UPS and inverters
Class-D amplifiers
Any switch mode power circuit requiring a half bridge driver
Related Literature
AN1896 “HIP2103, HIP2104 Evaluation Board User’s Guide”
AN1899
“HIP2103, HIP2104 3-phase, Full or Half Bridge
Motor Drive User’s Guide”
FIGURE 1. TYPICAL FULL BRIDGE APPLICATION FIGURE 2. HIP2104 SHUTDOWN CURRENT vs V
BAT
µController
HIP2104
VBAT
VCen
VCC
VDD
HI
LI
EPAD
LO
HS
HO
HB
VDen
VSS
DC
MOTOR
VBAT
VBAT
HI
LI
LO
HS
HO
HB
VSS
HIP2103
EPAD
VDD
VDD
3.5
4.0
4.5
5.0
5.5
I
BAT
(µA)
2.0
2.5
3.0
10 20 30 40
50
V
BAT
(VDC)
November 27, 2013
FN8276.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HIP2103, HIP2104
2
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November 27, 2013
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Block Diagram
Symbol Glossary
3.3V LDO
1 MSEC
DELAY
155C
OT
12V LDO
1 MSEC
DELAY
VDen
VDD
VCen
1
4V
UNDER
VOLTAGE
20 US
DELAY
20 US
DELAY
VDD HB
SLEEP
MODE
LEVEL
SHIFT
4V
UNDER
VOLTAGE
R
S
Q
HO
LO
HS
VSS
VDD
VBAT
LOGIC
BIAS
HI
LI
E
P
A
D
100K
100
100k
VCC
VBAT
Logic prevents
shoot-through
when LI and HI
are both high
Active pull-down
keeps bridge FET
off during UV, OT,
or sleep
2104
2103
2104
2103
10 US
DELAY
Time delay functional block with
rising edge prop delay (as indicated
by the rising arrow on the input) and
minimal falling edge delay.
2104
2103
Optional connections as indicated by
part numbers
HIP2104
HIP2103
2M
100k
100k
Boot FET
SEE FIGURES 3 AND 4 FOR
SLEEP MODE TIMING DETAILS
HIP2103, HIP2104
3
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November 27, 2013
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Pin Configurations
HIP2103
(8 LD 3x3 TDFN)
TOP VIEW
HIP2104
(12 LD 4x4 DFN)
TOP VIEW
EPAD
(VSS)
1
2
3
4
8
7
6
5
VDD
HI
LI
VSS
HB
HO
HS
LO
EPAD
(VSS)
1
2
3
4
12
11
10
9
8
VDen
VCen
VCC
VDD
HI
VBAT
HB
HO
HS
LO
6
5
LI
7 VSS
Pin Descriptions
HIP2103 HIP2104
SYMBOL DESCRIPTION
8 LD
TDFN
12 LD
DFN
- 1 VDen (HIP2104 only) VDD enable input, 3.3V or 5V logic compatible, V
BAT
tolerant. VDD output is turned on after
1ms debouncing period.
- 2 VCen (HIP2104 only) VCC enable input, 3.3V or 5V logic compatible. V
BAT
tolerant. VCC output is turned on after
1ms debouncing period.
- 3 VCC (HIP2104 only) 3.3V output voltage of linear regulator, 75mA. Enabled by VCen.
1 4 VDD (HIP2103) Input voltage 14V max.
(HIP2104) 0utput voltage of linear regulator, 12V nominal, 75mA. Enabled by VDen.
25HIHigh side input, 3.3V or 5V logic compatible. (HI -> HO).
36LILow side Input, 3.3V or 5V logic compatible. (LI -> LO).
47VSSSignal ground.
58LOLow side driver Output. (LI ->LO).
69HSHigh side FET Source connection (low side boot capacitor connection).
710HOHigh side driver Output. (HI -> HO)
811HBHigh side Boot capacitor.
- 12 VBAT (HIP2104 only) Positive battery (bridge voltage) connection.
EP EP EPAD Exposed Pad, must be connected to signal ground.

HIP2104FRAANZ-T7A

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers HV BRIDGE DRIVER
Lifecycle:
New from this manufacturer.
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