MPC9653A
Rev 4, 10/2004
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2004. All rights reserved.
3.3 V 1:8 LVCMOS PLL Clock
Generator
The MPC9653A is a 3.3 V compatible, 1:8 PLL based clock generator and
zero-delay buffer targeted for high performance low-skew clock distribution in
mid-range to high-performance telecom, networking and computing applications.
With output frequencies up to 125 MHz and output skews less than 150 ps the
device meets the needs of the most demanding clock applications.
Features
• 1:8 PLL based low-voltage clock generator
• Supports zero-delay operation
• 3.3 V power supply
• Generates clock signals up to 125 MHz
• PLL guaranteed to lock down to 145 MHz, output frequency = 36.25 MHz
• Maximum output skew of 150 ps
• Differential LVPECL reference clock input
• External PLL feedback
• Drives up to 16 clock lines
• 32-lead LQFP packaging
• 32-lead Pb-free Package Available
• Ambient temperature range 0°C to +70°C
• Pin and function compatible to the MPC953 and MPC9653
Functional Description
The MPC9653A utilizes PLL technology to frequency lock its outputs onto an
input reference clock. Normal operation of the MPC9653A requires the connec-
tion of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output
frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 25 to
62.5 MHz or 50 to 125 MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-4 or divide-by-8) and the ref-
erence clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The internal
VCO of the MPC9653A is running at either 4x or 8x of the reference clock frequency. The MPC9653A is guaranteed to lock in a
low power PLL mode in the high frequency range (VCO_SEL = 0) down to PLL = 145 MHz or F
ref
= 36.25 MHz.
The MPC9653A has a differential LVPECL reference input along with an external feedback input. The device is ideal for use
as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance.
The PLL_EN and BYPASS
controls select the PLL bypass configuration for test and diagnosis. In this configuration, the se-
lected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL by-
pass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply.
The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes
the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close
the phase locked loop, enabling the PLL to recover to normal operation.
The MPC9653A is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission
lines. For series terminated transmission lines, each of the MPC9653A outputs can drive one or two traces giving the devices an
effective fanout of 1:16. The device is packaged in a 7x7 mm
2
32-lead LQFP package.
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
MPC9653A
LOW VOLTAGE
3.3 V LVCMOS 1:8
PLL CLOCK GENERATOR
