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IPD50N06S2L13ATMA2

P1-P3P4-P6P7-P8
IPD50N06S2L-13
OptiMOS
®
Power-Transistor
Features
• N-channel Logic Level - Enhancement mode
• Automotive AEC Q101 qualified
• MSL1 up to 260°C peak reflow
• 175°C operating temperature
• Green package (lead free)
• Ultra low Rds(on)
• 100% Avalanche tested
Maximum ratings, at T
j
=25 °C, unless otherwise specified
Parameter Symbol Conditions Unit
Continuous drain current
1)
I
D
T
C
=25 °C, V
GS
=10 V
50 A
T
C
=100 °C,
V
GS
=10 V
2)
50
Pulsed drain current
2)
I
D,pulse
T
C
=25 °C
200
Avalanche energy, single pulse
E
AS
I
D
=50A
240 mJ
Gate source voltage
V
GS
±20 V
Power dissipation
P
tot
T
C
=25 °C
136 W
Operating and storage temperature
T
j
, T
stg
-55 ... +175 °C
IEC climatic category; DIN IEC 68-1 55/175/56
Value
V
DS
55 V
R
DS(on),max
(SMD version) 12.7
mΩ
I
D
50 A
Product Summary
PG-TO252-3-11
Type Package Marking
IPD50N06S2L-13 PG-TO252-3-11 PN06L13
Rev. 1.0 page 1 2006-07-18
IPD50N06S2L-13
Parameter Symbol Conditions Unit
min. typ. max.
Thermal characteristics
Thermal resistance, junction - case
R
thJC
- - 1.1 K/W
Thermal resistance, junction -
ambient, leaded
R
thJA
- - 100
SMD version, device on PCB
R
thJA
minimal footprint - - 75
6 cm
2
cooling area
3)
--50
Electrical characteristics, at T
j
=25 °C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage
V
(BR)DSS
V
GS
=0 V, I
D
= 1 mA
55 - - V
Gate threshold voltage
V
GS(th)
V
DS
=V
GS
, I
D
=80 µA
1.2 1.6 2.0
Zero gate voltage drain current
I
DSS
V
DS
=55 V, V
GS
=0 V,
T
j
=25 °C
- 0.01 1 µA
V
DS
=55 V, V
GS
=0 V,
T
j
=125 °C
2)
- 1 100
Gate-source leakage current
I
GSS
V
GS
=20 V, V
DS
=0 V
- 1 100 nA
Drain-source on-state resistance
R
DS(on)
V
GS
=4.5 V, I
D
=34 A
- 12.7 16.7
mΩ
Drain-source on-state resistance
R
DS(on)
V
GS
=10 V, I
D
=34 A
- 10.2 12.7 mΩ
Values
Rev. 1.0 page 2 2006-07-18
IPD50N06S2L-13
Parameter Symbol Conditions Unit
min. typ. max.
D
y
namic characteristics
2)
Input capacitance
C
iss
- 1800 - pF
Output capacitance
C
oss
- 508 -
Reverse transfer capacitance
C
rss
- 172 -
Turn-on delay time
t
d(on)
-9-ns
Rise time
t
r
-29-
Turn-off delay time
t
d(off)
-43-
Fall time
t
f
-12-
Gate Char
g
e Characteristics
2)
Gate to source charge
Q
gs
-68nC
Gate to drain charge
Q
gd
-1826
Gate charge total
Q
g
-5469
Gate plateau voltage
V
plateau
- 3.4 - V
Reverse Diode
Diode continous forward current
2)
I
S
- - 50 A
Diode pulse current
2)
I
S,pulse
- - 200
Diode forward voltage
V
SD
V
GS
=0 V, I
F
=50 A,
T
j
=25 °C
- 0.9 1.3 V
Reverse recovery time
2)
t
rr
V
R
=30 V, I
F
=I
S
,
di
F
/dt =100 A/µs
-52-ns
Reverse recovery charge
2)
Q
rr
V
R
=30 V, I
F
=I
S
,
di
F
/dt =100 A/µs
-99-nC
2)
Defined by design. Not subject to production test.
3)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm
2
(one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
1)
Current is limited by bondwire; with an RthJC=1.1 K/W the chip is able to carry 72 A. For detailed
information see Application Note ANPS071E at www.infineon.com/optimos
T
C
=25 °C
Values
V
GS
=0 V, V
DS
=25 V,
f =1 MHz
V
DD
=30 V, V
GS
=10 V,
I
D
=50 A, R
G
=3.6 Ω
V
DD
=44 V, I
D
=50 A,
V
GS
=0 to 10 V
Rev. 1.0 page 3 2006-07-18
P1-P3P4-P6P7-P8

IPD50N06S2L13ATMA2

Mfr. #:
Buy IPD50N06S2L13ATMA2
Manufacturer:
Infineon Technologies
Description:
MOSFET N-CHANNEL_55/60V
Lifecycle:
New from this manufacturer.
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