CCM-PFC
ICE1PCS01/G
Functional Description
Version 1.2 10 06 Feb 2007
Assuming the voltage loop is working and output
voltage is kept constant, the off duty cycle D
OFF
for a
CCM PFC system is given as
From the above equation, D
OFF
is proportional to V
IN
.
The objective of the current loop is to regulate the
average inductor current such that it is proportional to
the off duty cycle D
OFF
, and thus to the input voltage
V
IN
. Figure 11 shows the scheme to achieve the
objective.
Figure 11 Average Current Control in CCM
The PWM is performed by the intersection of a ramp
signal with the averaged inductor current at pin 5
(ICOMP). The PWM cycle starts with the Gate turn off
for a duration of T
OFFMIN
(250ns typ.) and the ramp is
kept discharged. The ramp is then allowed to rise after
T
OFFMIN
expires. The off time of the boost transistor
ends at the intersection of the ramp signal and the
averaged current waveform. This results in the
proportional relationship between the average current
and the off duty cycle D
OFF
.
Figure 12 shows the timing diagrams of T
OFFMIN
and the
PWM waveforms.
Figure 12 Ramp and PWM waveforms
3.6.4 Nonlinear Gain Block
The nonlinear gain block controls the amplitude of the
regulated inductor current. The input of this block is the
voltage at pin VCOMP. This block has been designed
to support the wide input voltage range (85-265VAC).
3.7 PWM Logic
The PWM logic block prioritizes the control input
signals and generates the final logic signal to turn on
the driver stage. The speed of the logic gates in this
block, together with the width of the reset pulse T
OFFMIN
,
are designed to meet a maximum duty cycle D
MAX
of
95% at the GATE output under 133kHz of operation.
In case of high input currents which result in Peak
Current Limitation, the GATE will be turned off
immediately and maintained in off state for the current
PWM cycle. The signal Toffmin resets (highest priority,
overriding other input signals) both the current limit
latch and the PWM on latch as illustrated in Figure 13.
Figure 13 PWM Logic
3.8 Voltage Loop
The voltage loop is the outer loop of the cascaded
control scheme which controls the PFC output bus
voltage V
OUT
. This loop is closed by the feedback
sensing voltage at VSENSE which is a resistive divider
tapping from V
OUT
. The pin VSENSE is the input of
OTA1 which has an internal reference of 5V. Figure 14
shows the important blocks of this voltage loop.
3.8.1 Voltage Loop Compensation
The compensation of the voltage loop is installed at the
VCOMP pin (see Figure 14). This is the output of OTA1
and the compensation must be connected at this pin to
ground. The compensation is also responsible for the
soft start function which controls an increasing AC input
current during start-up.
D
OFF
V
IN
V
OUT
------------- -=
t
ave(I
IN
) at ICOMP
ramp profile
GATE
drive
T
OFFMIN
250ns
V
CREF
(1)
V
RAMP
PWM
ramp
released
PWM cycle
(1)
V
CREF
is a function of V
ICOMP
t
G1
R
S
L1
R
S
L2
Peak Current
Limit
Current Loop
PWM on signal
Toffmin
250ns
Current
Limit Latch
PWM on
Latch
HIGH =
turn GATE on
Q
Q
