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ICE1PCS01G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
CCM-PFC
ICE1PCS01/G
Functional Description
Version 1.2 7 06 Feb 2007
3.1 General
The ICE1PCS01/G is a 8 pin control IC for power factor
correction converters. It comes in both DIP and DSO
packages and is suitable for wide range line input
applications from 85 to 265 VAC. The IC supports
converters in boost topology and it operates in
continuous conduction mode (CCM) with average
current control.
The IC operates with a cascaded control; the inner
current loop and the outer voltage loop. The inner
current loop of the IC controls the sinusoidal profile for
the average input current. It uses the dependency of
the PWM duty cycle on the line input voltage to
determine the corresponding input current. This means
the average input current follows the input voltage as
long as the device operates in CCM. Under light load
condition, depending on the choke inductance, the
system may enter into discontinuous conduction mode
(DCM). In DCM, the average current waveform will be
distorted but the resultant harmonics are still low
enough to meet the Class D requirement of IEC 1000-
3-2.
The outer voltage loop controls the output bus voltage.
Depending on the load condition, OTA1 establishes an
appropriate voltage at VCOMP pin which controls the
amplitude of the average input current.
The IC is equipped with various protection features to
ensure safe operating condition for both the system
and device. Important protection features are namely
Brown-out protection, Current Limitation and Output
Under-voltage Protection.
3.2 Power Supply
An internal under voltage lockout (UVLO) block
monitors the VCC power supply. As soon as it exceeds
11.2V and the voltage at pin 6 (VSENSE) is >0.8V, the
IC begins operating its gate drive and performs its Soft-
Start as shown in Figure 3.
.
Figure 3 State of Operation respect to VCC
If VCC drops below 10.2V, the IC is off. The IC will then
be consuming typically 200µA, whereas consuming
18mA during normal operation.
The IC can be turned off and forced into standby mode
by pulling down the voltage at pin 6 (VSENSE) to lower
than 0.8V. The current consumption is reduced to 3mA
in this mode.
3.3 Start-up (Soft-Start)
Figure 4 and 5 show the operation of OTA1 during
startup. It sources a constant 10.8µA into the
compensation network at pin 5 (VCOMP). The voltage
at this pin rises linearly and so does the amplitude of
the input current. As soon as the output voltage V
OUT
reaches 80% of its rated level, the startup procedure is
finished and the normal voltage control takes over. In
normal operation, the IC operates with a higher
maximum current at OTA1 and therefore with a higher
voltage loop gain in order to improve the dynamic
behavior of the device.
.
Figure 4 Soft Start Circuit
Figure 5 Soft Start with controlled current
The advantage of this technique is a soft-start function
with lower stress for the boost diode but without the risk
of audible noise.
V
CC
V
VSENSE
> 0,8 V
V
VSENSE
< 0,8 V
11.2 V
10.5 V
t
OFF
Soft
start
Open loop/
Standby
Normal
Operation
IC's
State
OFF
V
VSENSE
> 0,8 V
Normal
Operation
VCOMP
C5
C4
VSENSE
OTA1
5V
ICE1PCS01/G
C3
Open-Loop
Protect
(OLP)
0.8V
R3 + R4
R4
x V
OUT
)
(
10.8uA during
Soft Start
R6
S1
4.0V
Soft Start
Soft Start
Normal Operation
av(I
IN
)
V
OUT
< 80% rated V
OUT
> 80% rated
t
3 Functional Description
CCM-PFC
ICE1PCS01/G
Functional Description
Version 1.2 8 06 Feb 2007
3.4 System Protection
The IC provides several protection features in order to
ensure the PFC system in safe operating range.
Depending on the input line voltage (V
IN
) and output
bus voltage (V
OUT
), Figure 6 and 7 show the conditions
when these protections are active.
Figure 6 V
IN
Related Protection Features
Figure 7 V
OUT
Related Protection Features
The following sections describe the functionality of
these protection features.
3.4.1 Brown-Out Protection (BOP)
Brown-out occurs when the input voltage V
IN
falls below
the minimum input voltage of the design (i.e. 85V for
universal input voltage range) and the VCC has not
entered into the V
CCUVLO
level yet. For a system without
BOP, the boost converter will increasingly draw a
higher current from the mains at a given output power
which may exceed the maximum design values of the
input current. The ICE1PCS01/G limits internally the
current drawn from the mains and therefore also limits
the input power. The difference of input and output
power will result in decreasing output voltage. If the
condition prolongs, the decreasing V
OUT
will terminate
in output under voltage condition (OUV, 50% of rated),
and the IC will be shut down (See section 3.4.5).
Figure 8 shows the occurrence of BOP in respect to the
ISENSE voltage.
Figure 8 BOP, SOC and PCL Protection as function
of V
ISENSE
The V
IN
threshold for BOP to occur is dependent on the
voltage at ISENSE and thus the output power. The
rated output power with a minimum V
IN
(V
INMIN
) is
Due to the internal parameter tolerance, the maximum
power with V
INMIN
before BOP occurs is
And the BOP takes over the normal operation under
rated output power latest at an input voltage of
3.4.2 Soft Over Current Control (SOC)
The IC is designed not
to support any output power
that corresponds to a voltage lower than -0.73V at the
ISENSE pin. A further increase in the inductor current,
which results in a lower ISENSE voltage, will activate
the Soft Over Current Control (SOC). This is a soft
control as it does not directly switch off the gate drive
like the PCL. It acts on the nonlinear gain block to result
in a reduced PWM duty cycle.
3.4.3 Peak Current Limit (PCL)
The IC provides a cycle by cycle peak current limitation
(PCL). It is active when the voltage at pin 3 (ISENSE)
reaches -1.08V. This voltage is amplified by OP1 by a
factor of -1.43 and connected to comparator C2 with a
reference voltage of 1.5V as shown in Figure 9. A
deglitcher with 300ns after the comparator improves
noise immunity to the activation of this protection.
t
V
INMIN
(1)
V
IN
(VAC)
VCC > V
CCUVLO
Normal
Operation
IC OFF
BOP
VCC<V
CCUVLO
(1)
V
INMIN
where BOP activates depends on the output power
IC’s
State
t
V
OUT
PCL / SOC
16%
50%
100%
OLP OLPOUV
105%
OVP
V
OUT,Rated
V
ISENSE
-0.6V -0.73V -1.08V
Normal
Operation
SOC PCL
P
OUT
(rated)
BOP
IC’s
State
0
(BOP occurs at V
ISENSE
= -0.6V Max)
P
OUT
(max)
P
OUT
rated()V
INMIN
0.6
R1 2⋅
-------------------×=
P
OUT
max()V
INMIN
0.73
R1 2⋅
-------------------×=
V
BOPMAX
P
OUT
rated()
R1 2⋅
0.73
-------------------×=
CCM-PFC
ICE1PCS01/G
Functional Description
Version 1.2 9 06 Feb 2007
Figure 9 Peak Current Limit (PCL)
3.4.4 Open Loop Protection / Input Under
Voltage Protect (OLP)
Whenever VSENSE voltage falls below 0.8V, or
equivalently V
OUT
falls below 16% of its rated value, it
indicates an open loop condition (i.e. VSENSE pin not
connected) or an insufficient input voltage V
IN
for
normal operation. In this case, most of the blocks within
the IC will be shutdown. It is implemented using
comparator C3 with a threshold of 0.8V as shown in the
IC block diagram in Figure 2.
3.4.5 Output Under Voltage Detection (OUV)
In the event of main interrupt or brown-out condition,
the PFC system is not able to deliver the rated output
power. This will cause the output voltage V
OUT
to drop
below its rated value. The IC provides an output under
voltage detection that checks if V
OUT
is falling below
50% of its rated value. Comparator C4 as shown in the
device block diagram (Figure 2) senses the voltage at
pin 6 (VSENSE) with a reference of 2.5V. If comparator
C4 trips, the IC will be shut down as in OLP. The IC will
be ready to restart if there is sufficient V
IN
to pull V
OUT
out of OLP.
3.4.6 Over-Voltage Protection (OVP)
Whenever V
OUT
exceeds the rated value by 5%, the
over-voltage protection OVP is active as shown in
Figure 7. This is implemented by sensing the voltage at
pin VSENSE with respect to a reference voltage of
5.25V. A VSENSE voltage higher than 5.25V will
immediately reduce the output duty cycle, bypassing
the normal voltage loop control. This results in a lower
input power to reduce the output voltage V
OUT
.
3.5 Frequency Setting
The switching frequency of the PFC converter can be
set with an external resistor R5 at FREQ pin. The pin
voltage V
FREQ
is typically 2.5V. The corresponding
capacitor for the oscillator is integrated in the device
and the R5/frequency relationship is given at the
“Electrical Characteristic” section. The
recommended operating frequency range is from
50kHz to 250kHz. As an example, a R5 of 33kΩ at pin
FREQ will set a switching frequency F
SW
of 133kHz
typically.
3.6 Average Current Control
3.6.1 Complete Current Loop
The complete system current loop is shown in Figure
10.
Figure 10 Complete System Current Loop
It consists of the current loop block which averages the
voltage at pin ISENSE, resulted from the inductor
current flowing across R1. The averaged waveform is
compared with an internal ramp in the ramp generator
and PWM block. Once the ramp crosses the average
waveform, the comparator C1 turns on the driver stage
through the PWM logic block. The Nonlinear Gain block
defines the amplitude of the inductor current. The
following sections describe the functionality of each
individual blocks.
3.6.2 Current Loop Compensation
The compensation of the current loop is done at the
ICOMP pin. This is the OTA2 output and a capacitor C3
has to be installed at this node to ground (see Figure
10). Under normal mode of operation, this pin gives a
voltage which is proportional to the averaged inductor
current. This pin is internally shorted to 5V in the event
of IC shuts down when OLP and UVLO occur.
3.6.3 Pulse Width Modulation (PWM)
The IC employs an average current control scheme in
continuous conduction mode (CCM) to achieve the
power factor correction.
ISENSE
ICE1PCS01/G
R1
R2
I
INDUCTOR
OP1
1.43x
Current Limit
300ns
C2
Deglitcher
Turn Off
Driver
1.5V
Full-wave
Rectifier
R
S
ICE1PCS01/G
Vout
L1
C2
R3
R4
Gate
Driver
D1
From
Full-wave
Retifier
GATE
R1
R2
OTA2
ICOMP
4V
Current Loop
Compensation
Current Loop
Nonlinear
Gain
1.1mS
+/-50uA (linear range)
C3
S2
Fault
ISENSE
C1
PWM
Comparator
PWM Logic
Q
Input From
Voltage Loop
voltage
proportional to
averaged
Inductor current
R7
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

ICE1PCS01G

Mfr. #:
Buy ICE1PCS01G
Manufacturer:
Infineon Technologies
Description:
Power Factor Correction - PFC STANDALONE PFC CTRLR CCM BRN-OUT PROTECT
Lifecycle:
New from this manufacturer.
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