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PI3VDP411LSRZBEX

P1-P3P4-P6P7-P9P10-P10
7
www.pericom.com PS9060A 08/23/11
PI3VDP411L SR
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shier)
Truth Table (Slew Rate control function)
SR1 SR0 Rise/Fall Time (Typ)
1 1 140ps
1 0 130ps
0 1 120ps
0 0 110ps
Test Setup Condition
V
DD
= 3.3V, Ambient temperture 25°C
Rise/Fall time is from 20% to 80% on Rising/Falling edge
Date rate: 620 Mbps
Input: 1V dierential peak-to-peak clock pattern
Equalization : 3dB
Table 1: OE Pin Description
OE# Device State Comments
Asserted (low voltage)
Dierential input buers and output buers
enabled. Input impedance = 50Ω
Normal functioning state for IN_D to OUT_D
level shiing function.
Unasserted (high voltage)
Low-power state.
Dierential input buers and termination
are disabled.
Dierential inputs are in a high
impedance state.
OUT_D level-shiing outputs are
disabled.
OUT_D level-shiing outputs are in high
impedance state.
Internal bias currents are turned o.
Intended for lowest power condition when:
No display is plugged in or
e level shied data path is disabled
HPD_SINK input and HPD_SOURCE
output are not aected by OE# SCL_
SOURCE, SCL_SINK, SDA_SOURCE
and SDA_SINK signals and functions
are not aected by OE#
8
www.pericom.com PS9060A 08/23/11
PI3VDP411L SR
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shier)
Table 2: Dierential Output Characteristics for TMDS_OUT signals
Symbol Parameter Min Ty p Max Units Comments
V
H
Single-ended high level
output voltage
V
DD
-10mV V
DD
V
DD
+10mV
V
V
DD
is the DC termination volt-
age in the HDMI or DVI Sink.
V
DD
is nominally 3.3V
V
L
Single-ended low level
output voltage
V
DD
-60 0mV V
DD
-50 0mV V
DD
-400mV
V
e open-drain output pulls
down from V
DD
.
V
SWING
Single ended output swing
voltage
425 500 600 mV
Swing down from TMDS termi-
nation voltage (3.3V ±10%)
I
OFF
Single-ended current in
high-Z state
50 µA
Measured with TMDS outputs
pulled up to V
DD
Max _(3.6V)
through 50Ω resistors.
T
SKEW-INTRA
Intra-pair dierential
skew
30 ps
is dierential skew budget is
in addition to the skew present-
ed between D+ and D- paired
input pins. HDMI revision 1.3
source allowable intrapair skew
is 0.15 T
bit
.
T
SKEW-INTER
Inter-pair lane-to-lane
output skew
100 ps
is lane-to-lane skew budget
is in addition to skew between
dierential input pairs
T
JIT
Jitter added to TMDS
signals
25 ps
Jitter budget for TMDS signals
as they pass through the level
shier. 25ps = 0.056 T
bit
at 2.25
Gb/s
TMDS output oscillation elimination
e inputs do not incorporate a squelch circuit. erefore, we recommend the input to be externally biased to prevent output oscilla-
tion. Pericom recommends to add a 1.5Kohm pull-up to the CLK- input.
TMDS Input Fail-Safe Recommendation
1.5Kohm
R
INT
VBIAS
R
INT
DMDP
Receiver
TMDS
Driver
S
S
S
S
R
T
R
T
AV
DD
3.3V
9
www.pericom.com PS9060A 08/23/11
PI3VDP411L SR
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shier)
Table 3: HPD Characteristics
Symbol Parameter Min Typ Max Units Comments
V
IH-HPD
Input High Level 2.0 5.0 5.3 V
Low-speed input changes state on cable plug/
unplug
V
IL-HPD
HPD_sink Input Low
Level
0 0.8 V
I
IN-HPD
HPD_sink Input Leakage
Current
70 µA
Measured with HPD_sink at V
IH-HPD
max
and V
IL-HPD
min
V
OH-HPD
HPD_source Output
High-Level
2.5
V
DD
V
V
DD
= 3.3V ±10%
I
OH
= -4mA(MIN) / -8mA(MAX)
V
OL-HPD
HPD_source Output Low-
Level
0 0.4 V
I
OL
= 4mA(MIN) / 8mA(MAX)
T
HPD
HPD_sink to HPD_source
propagation delay
200 ns
Time from HPD_sink changing state to
HPD_source changing state. Includes HPD_
source rise/fall time
T
RF-HPDB
HPD_source rise/ fall time 1 20 ns
Time required to transition from V
OH- HPDB
to V
OL-HPDB
or from V
OL-HPDB
to V
OH-HPDB
Table 4: OE# Input, DDC_EN
Symbol Parameter Min Typ Max Units Comments
V
IH
Input High Level 2.0
V
DD
V
TMDS enable input changes state on cable
plug/unplug
V
IL
Input Low Level 0 0.8 V
I
IN
Input Leakage Current 10 µA
Measured with input at V
IH-EN
max and
V
IL-EN
min
Table 5: Termination Resistor
Symbol Parameter Min Typ Max Units Comments
R
HPD
HPD_sink input pull-
down resistor.
100K Ω
Guarantees HPD_sink is LOW when no
display is plugged in.
P1-P3P4-P6P7-P9P10-P10

PI3VDP411LSRZBEX

Mfr. #:
Buy PI3VDP411LSRZBEX
Manufacturer:
Diodes Incorporated
Description:
Video ICs Dual Mode DP to TMDS electrical bridge
Lifecycle:
New from this manufacturer.
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