LTC2351-12
10
235112fa
BLOCK DIAGRAM
2
OGND
1
SD0
3
OV
DD
3V
+
4
5
24
23
S & H
+
7
6
9
12 13
16
19
8
S & H
EXPOSED PAD GND V
REF
10μF
CH0
CH0
+
CH1
CH1
+
+
10
11
S & H
+
14
15
S & H
CH2
CH2
+
CH3
CH3
+
+
17
18
S & H
+
20
21
S & H
CH4
CH4
+
CH5
CH5
+
10μF
0.1μF
DGND
32
SCK
30
CONV
SEL2
SEL1 SEL0
THREE-
STATE
SERIAL
OUTPUT
PORT
MUX
2.5V
REFERENCE
TIMING
LOGIC
V
CC
25
3V
V
DD
235112 BD
1.5Msps
12-BIT ADC
12-BIT LATCH 5
12-BIT LATCH 4
12-BIT LATCH 3
12-BIT LATCH 2
12-BIT LATCH 1
12-BIT LATCH 0
26 27
BIP
29 28 31
2233
0.1μF
LTC2351-12
11
235112fa
TIMING DIAGRAMS
LTC2351-12 Timing Diagram
235112 TD01
66 67
68
69 70 71 72 757473 76 77 78 79 80 81 82 83 84 85 86 87
88
89 90 91 92 93 9594 96 97 98 1 2 3 4 5 6
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH4
D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 D0 X XD9
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH5
SAMPLE
Hi-Z
D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 D0 X XD9
D11
Back to SAMPLE mode if SELx = 011
Back to SAMPLE mode if SELx = 100
t
8
t
6
t
4
t
6
t
8
t
CONV
12-BIT DATA WORD 12-BIT DATA WORD
t
THROUGHPUT
to SAMPLE mode if SELx = 001
34 35 383736 39 40 41 42 43 44 45 46 47 48 49 50
51
52 53 54 55 56 5857 59 60 61 62 63 64 65
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH2
D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 D0 X XD9
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH3
D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 D0 X XD9
Back to SAMPLE mode if SELx = 010
t
CONV
12-BIT DATA WORD 12-BIT DATA WORD
t
THROUGHPUT
SCK
CONV
INTERNAL
S/H STATUS
SDO
t
3
t
1
19897 2 3 4 5 6 7 8 9 10 11 12 13
14
15 16 17 18 19 2120 22 23 24 25 26 27 28 29 30
31
32 33
t
2
t
6
t
8
t
10
t
9
t
8
t
4
SAMPLE HOLD
Hi-Z
Hi-Z
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH1
D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 D0 X XD9 D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 D0 X XD9
94 95 96
Back toBack to SAMPLE mode if SELx = 000
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH0
t
CONV
12-BIT DATA WORD 12-BIT DATA WORD
t
THROUGHPUT
D10 D9 D8
LTC2351-12
12
235112fa
Nap Mode and Sleep Mode Waveforms
SCK to SDO Delay
TIMING DIAGRAMS
SCK
CONV
NAP
SLEEP
V
REF
t
1
t
11
t
1
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS
235112 TD02
t
8
t
10
SCK
SDO
235112 TD03
V
IH
V
OH
V
OL
t
9
SCK
SDO Hi-Z
V
IH

LTC2351CUH-12#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-Bit, 6-Channel 1.5Msps Simultaneous Samping ADC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union