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LTC2351IUH-12#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
LTC2351-12
19
235112fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
APPLICATIONS INFORMATION
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693)
5.00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
31
1
2
32
BOTTOM VIEW—EXPOSED PAD
3.50 REF
(4-SIDES)
3.45 ± 0.10
3.45 ± 0.10
0.75 ± 0.05
R = 0.115
TYP
0.25 ± 0.05
(UH32) QFN 0406 REV D
0.50 BSC
0.200 REF
0.00 – 0.05
0.70 ±0.05
3.50 REF
(4 SIDES)
4.10 ±0.05
5.50 ±0.05
0.25 ± 0.05
PACKAGE OUTLINE
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
R = 0.05
TYP
3.45 ± 0.05
3.45 ± 0.05
PACKAGE DESCRIPTION
The buffered serial port in the TMS320C54x has direct
access to a 2kB segment of memory. The ADC’s serial
data can be collected in two alternating 1kB segments,
in real time, at the full 1.5Msps conversion rate of the
LTC2351-12. The DSP assembly code sets frame sync
mode at the BFSR pin to accept an external positive going
pulse and the serial clock at the BCLKR pin to accept an
external positive edge clock. Buffers near the LTC2351-12
may be added to drive long tracks to the DSP to prevent
corruption of the signal to LTC2351-12. This confi guration
is adequate to traverse a typical system board, but source
resistors at the buffer outputs and termination resistors
at the DSP, may be needed to match the characteristic
impedance of very long transmission lines. If you need
to terminate the SDO transmission line, buffer it fi rst with
one or two 74ACxx gates. The TTL threshold inputs of the
DSP port respond properly to the 3V swing used with the
LTC2351-12.
LTC2351-12
20
235112fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
LT 0209 REV A • PRINTED IN USA
PRE
V
CC
1k
1k50Ω
V
CC
NL17SZ74
CONVERT ENABLE
NC7SVU04P5X
MASTER CLOCK
0.1μF
CONV
2351-12
CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
DQ
Q
CLR
1408 TA02
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TYPICAL APPLICATION
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LTC1403-1/LTC1403A-1 12-/14-Bit, 2.8Msps Serial ADC 3V, 15mW, Bipolar Inputs, MSOP Package
LTC1405 12-Bit, 5Msps Parallel ADC 5V, Selectable Spans, 115mW
LTC1407/LTC1407A 12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 14mW, 2-Channel Unipolar Input Range
LTC1407-1/LTC1407A-1 12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 14mW, 2-Channel Bipolar Input Range
LTC1411 14-Bit, 2.5Msps Parallel ADC 5V, Selectable Spans, 80dB SINAD
LTC1412 12-Bit, 3Msps Parallel ADC ±5V Supply, ±2.5V Span, 72dB SINAD
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LTC1608 16-Bit, 500ksps Parallel ADC ±5V Supply, ±2.5V Span, 90dB SINAD
LTC1609 16-Bit, 250ksps Serial ADC 5V Confi gurable Bipolar/Unipolar Inputs
LTC1864/LTC1865
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DACs
LTC1592 16-Bit, Serial SoftSpan™ I
OUT
DAC ±1LSB INL/DNL, Software Selectable Spans
LTC1666/LTC1667/
LTC1668
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References
LT1460-2.5 Micropower Series Voltage Reference 0.10% Initial Accuracy, 10ppm Drift
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SoftSpan is a trademark of Linear Technology Corporation.
Low-Jitter Clock Timing with RF Sine Generator Using Clock
Squaring/Level Shifting Circuit and Re-Timing Flip-Flop
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

LTC2351IUH-12#TRPBF

Mfr. #:
Buy LTC2351IUH-12#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-Bit, 6-Channel 1.5Msps Simultaneous Samping ADC
Lifecycle:
New from this manufacturer.
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