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LTC2351IUH-12#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
LTC2351-12
4
235112fa
POWER REQUIREMENTS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at T
A
= 25°C. With internal reference, V
DD
= V
CC
= 3V.
TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at T
A
= 25°C. V
DD
= 3V.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
, V
CC
Supply Voltage 2.7 3.0 3.6 V
I
DD
+ I
CC
Supply Current Active Mode, f
SAMPLE
= 1.5Msps
Active Mode, f
SAMPLE
= 1.5Msps (LTC2351H-12)
Nap Mode
Nap Mode (LTC2351H-12)
Sleep Mode
l
l
l
l
5.5
6
1.5
1.8
4.0
8
9
2
2.5
15
mA
mA
mA
mA
μA
P
D
Power Dissipation Active Mode with SCK, f
SAMPLE
= 1.5Msps 16.5 mW
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE(MAX)
Maximum Sampling Rate per Channel
(Conversion Rate)
l
250 kHz
t
THROUGHPUT
Minimum Sampling Period (Conversion + Acquisiton Period)
l
4μs
t
SCK
Clock Period (Note 16)
l
40 10000 ns
t
CONV
Conversion Time (Notes 6, 17) 96 SCLK cycles
t
1
Minimum High or Low SCLK Pulse Width (Note 6) 2 ns
t
2
CONV to SCK Setup Time (Notes 6, 10) 3 10000 ns
t
3
SCK Before CONV (Note 6) 0 ns
t
4
Minimum High or Low CONV Pulse Width (Note 6) 4 ns
t
5
SCK↑ to Sample Mode
(Note 6) 4 ns
t
6
CONV↑ to Hold Mode
(Notes 6, 11) 1.2 ns
t
7
96th SCK↑ to CONV↑ Interval (Affects Acquisition Period)
(Notes 6, 7, 13) 45 ns
t
8
Minimum Delay from SCK to Valid Bits 0 Through 11 (Notes 6, 12) 8 ns
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifi cations which apply over the
full operating temperature range, otherwise specifi cations are at T
A
= 25°C. V
DD
= V
CC
= 3V.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
High Level Input Voltage V
DD
= 3.3V
l
2.4 V
V
IL
Low Level Input Voltage V
DD
= 2.7V
l
0.6 V
I
IN
Digital Input Current V
IN
= 0V to V
DD
l
±10 μA
C
IN
Digital Input Capacitance 5pF
V
OH
High Level Output Voltage V
DD
= 3V, I
OUT
= –200μA
l
2.5 2.9 V
V
OL
Low Level Output Voltage V
DD
= 2.7V, I
OUT
= 160μA
V
DD
= 2.7V, I
OUT
= 1.6mA
l
0.05
0.4
V
V
I
OZ
Hi-Z Output Leakage D
OUT
V
OUT
= 0V and V
DD
l
±10 μA
C
OZ
Hi-Z Output Capacitance D
OUT
1pF
I
SOURCE
Output Short-Circuit Source Current V
OUT
= 0V, V
DD
= 3V 20 mA
I
SINK
Output Short-Circuit Sink Current V
OUT
= V
DD
= 3V 15 mA
LTC2351-12
5
235112fa
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 2: All voltage values are with respect to ground GND.
Note 3: When these pins are taken below GND or above V
DD
, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V
DD
without latchup.
Note 4: Offset and range specifi cations apply for a single-ended CH0
+
– CH5
+
input with CH0
–
– CH5
–
grounded and using the internal 2.5V
reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
defi ned as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band. Linearity is tested for CH0 only.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defi ned for the voltage difference
between CHx
+
and CHx
–
, x = 0 to 5.
Note 9: The absolute voltage at CHx
+
and CHx
–
must be within this range.
Note 10: If less than 3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
96th rising clock and it is ended by the rising edge of CONV.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10μF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5V
P-P
input sine wave.
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17: The conversion process takes 16 clocks for each channel that is
enabled, up to 96 clocks for all 6 channels.
TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at T
A
= 25°C. V
DD
= 3V.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
9
SCK↑ to Hi-Z at SDO
(Notes 6, 12) 6 ns
t
10
Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns
t
11
V
REF
Settling Time After Sleep-to-Wake Transition (Notes 6, 14) 2 ms
LTC2351-12
6
235112fa
SFDR vs Input Frequency SNR vs Input Frequency
100kHz Unipolar Sine Wave 8192
Point FFT Plot
FREQUENCY (MHz)
50
68
62
56
92
86
80
74
235112 G04
SFDR (dB)
0.1
10
1
FREQUENCY (MHz)
0.1
SNR (dB)
53
59
56
62
65
68
71
110
235112 G05
74
FREQUENCY (kHz)
0
MAGNITUDE (dB)
–20
0
50 100 125
235112 G06
–100
–40
–120
–110
–90
–70
–50
–30
–10
–60
–80
25 75
100kHz Bipolar Sine Wave 8192
Point FFT Plot
Differential Linearity
vs Output Code, Unipolar Mode
Integral Linearity
vs Output Code, Unipolar Mode
FREQUENCY (kHz)
0
MAGNITUDE (dB)
–20
–10
–30
–0
50
100
125
235112 G07
–100
–40
–50
–120
–110
–60
–70
–80
–90
25
75
OUTPUT CODE
0
–1
DIFFERENTIAL LINEARITY (LSB)
–0.8
–0.4
–0.2
0
1
0.4
1024
2048
2560
235112 G08
–0.6
0.6
0.8
0.2
512 1536
3072
3584
4096
OUTPUT CODE
0
–1
INTEGRAL LINEARITY (LSB)
–0.8
–0.4
–0.2
0
1
0.4
1024 2048 2560
235112 G09
–0.6
0.6
0.8
0.2
512 1536 3072 3584 4096
TYPICAL PERFORMANCE CHARACTERISTICS
V
DD
= 3V, T
A
= 25°C
SINAD vs Input Frequency
THD, 2nd and 3rd
vs Input Frequency
THD, 2nd and 3rd
vs Input Frequency
FREQUENCY (MHz)
53
62
59
56
74
71
68
65
235112 G01
SINAD (dB)
0.1
10
1
2nd
FREQUENCY (MHz)
0.1
–110
THD, 2nd, 3rd (dB)
–98
–86
–74
–62
110
235112 G02
–50
–104
–92
–80
–68
–56
UNIPOLAR SINGLE-ENDED
THD
3rd
FREQUENCY (MHz)
0.1
–116
THD, 2nd, 3rd (dB)
–104
–92
–80
–68
110
235112 G03
–50
–100
–98
–86
–74
–62
–56
BIPOLAR SINGLE-ENDED
THD
3rd
2nd
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

LTC2351IUH-12#TRPBF

Mfr. #:
Buy LTC2351IUH-12#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-Bit, 6-Channel 1.5Msps Simultaneous Samping ADC
Lifecycle:
New from this manufacturer.
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