96D2-1G800NN-TRL1 Datasheet 96D2-1G800NN-TRL1 | P4-P6

240PIN DDR2 800 Unbuffered DIMM 0.72”

1024MB With 128Mx8 CL6

Transcend Information Inc.

Block Diagram

DQS0

DM0

/DQS0

/CS0

DQS1

DM1

/DQS1

/CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS2

DM2

/DQS2

/CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS3

DM3

/DQS3

/CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS4

DM4

/DQS

/CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS5

DM5

/DQS5

/CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS6

DM6

/DQS

/CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS7

DM7

/DQS7

/CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ 0

DQ 1

DQ 2

DQ 3

DQ 4

DQ 5

DQ 6

DQ 7

DQ 8

DQ 9

DQ 11

DQ 12

DQ 13

DQ 14

DQ 15

DQ 16

DQ 17

DQ 19

DQ 20

DQ 21

DQ 32

DQ 33

DQ 34

DQ 35

DQ 36

DQ 37

DQ 39

DQ 40

DQ 41

DQ 42

DQ 43

DQ 44

DQ 45

DQ 46

DQ 47

VDDSPD

VDD/VDDQ

VREF

VSS

EEPROM

U1~U8

SDA

SCL

SA0 SA1 SA2

EEPROM

Note:

1.DQ,DM,DQS & /DQS resistors :22 Ohm 5%

2.Bx,Ax,/RAS, /CAS & /WE resistors :10 Ohm 5%

CK0,/CK0

A0~A13

BA0~BA2

CKE0

/RAS

/CAS

/WE

ODT0

U1~U

U1~U8

CK1,/CK1

CK2,/CK2

U4~U5

U1~U3

U6~U8

/CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ 24

DQ 25

DQ 26

DQ 27

DQ 28

DQ 29

DQ 30

DQ 31

DQ 56

DQ 57

DQ 58

DQ 59

DQ 60

DQ 61

DQ 62

DQ 63

DQ 48

DQ 49

DQ 50

DQ 51

DQ 52

DQ 53

DQ 54

DQ 55

This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either

expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes

in specifications at any time without prior notice.

240PIN DDR2 800 Unbuffered DIMM 0.72”

1024MB With 128Mx8 CL6

Transcend Information Inc.

Absolute Maximum DC Ratings

Parameter Symbol Value Unit Notes

Voltage on V

relative to Vss VDD -1.0 ~ 2.3 V 1

Voltage on V

DDQ

pin relative to Vss VDDQ -0.5 ~ 2.3 V 1

Voltage on V

DDL

pin relative to Vss VDDL -0.5 ~ 2.3 V 1

Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 2.3 V 1

Storage temperature T

STG

-55~+100 °C 1, 2

1.Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the

stress rating only and functional operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect reliability.

Note:

2.Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the

measurement conditions, please refer to JESD51-2 standard.

AC & DC Operating Conditions

Recommended DC operating conditions (SSTL –1.8)

Rating

Parameter Symbol

Min Typ. Max

Unit

Notes

Supply voltage VDD 1.7 1.8 1.9 V

Supply voltage for DLL VDDL 1.7 1.8 1.9 V

Supply voltage for Output VDDQ 1.7 1.8 1.9 V

I/O Reference voltage VREF 0.49*V

DDQ

0.50*VDDQ

0.51*VDDQ V

2,3

I/O Termination voltage VTT V

REF

-0.04 V

REF

+0.04 V

DC Input logic high VIH

(DC)

REF

+0.125

- V

DDQ

+0.3 V

DC Input logic low VIL

(DC)

-0.3 - V

REF

-0.125 V

There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all

conditions VDDQ must be less than or equal to VDD.

1. AC parameters are measured with VDD, VDDQ and VDDDL tied together.

2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically

the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to

track variations in VDDQ.

3. Peak to peak AC noise on VREF may not exceed +/-2% VREF (DC).

4. VTT of transmitting device must track VREF of receiving device.

Note:

Operating Temperature Condition

Parameter Symbol

Rating

Unit

Note

Operating Temperature TOPER

0 to 85 °C

1, 2

1.Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the

measurement conditions, please refer to JESD51.2 standard.

Note:

2. At 0 - 85°C, operation temperature range are the temperature which all DRAM specification will be supported.

240PIN DDR2 800 Unbuffered DIMM 0.72”

1024MB With 128Mx8 CL6

Transcend Information Inc.

IDD Specification parameters Definition

( IDD values are for full operating range of voltage and Temperature)

Parameter Symbol

Max.

Unit

Note

Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD),

tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

IDD0 600 mA

Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 4, CL =

CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =

tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus

inputs are SWITCHING; Data pattern is same as IDD4W

IDD1 680 mA

Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW;

Other control and address bus inputs are STABLE; Data bus inputs are FLOATING

IDD2P

120 mA

Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,

CS\ is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are

FLOATING

IDD2Q

240 mA

Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is

HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are

SWITCHING

IDD2N

280 mA

Fast PDN Exit MRS(12) = 0mA

IDD3P-F

280

Active power - down current;

All banks open; tCK

= tCK(IDD); CKE is LOW; Other control and address

bus inputs are STABLE; Data bus inputs are

FLOATING

Slow PDN Exit MRS(12) = 1mA

IDD3P-S

144

Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD),

tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Other control

and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

IDD3N

440 mA

Operating burst read current; All banks open, Continuous burst reads, IOUT =

0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =

tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs

are SWITCHING; Data pattern is same as IDD4W

IDD4R

1,080

Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL

= CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is

HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING IDD4R

IDD4W

920 mA

Burst Auto refresh current;

tCK = tCK(IDD); Refresh command at every tRFC(IDD)

interval; CKE is HIGH, CS\ is HIGH between valid commands; Other control and

address bus inputs are SWITCHING; Data bus inputs are SWITCHING

IDD5 1,160

Self refresh current; CK and CK\ at 0V; CKE 0.2V; Other control and address

bus inputs are FLOATING; Data bus inputs are FLOATING

IDD6 120 mA

Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK =tCK(IDD), tRC = tRC

(IDD),

tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid

commands; Address bus inputs are STABLE during Deselects; Data pattern is same

as IDD4R; Refer to the following page for detailed timing conditions

IDD7 2,000

Note: 1. Module I

was calculated on the basis of component I

and can be differently measured according to DQ

loading capacitor.

P1-P3 P4-P6 P7-P9 P10-P11

96D2-1G800NN-TRL1

Mfr. #:

Buy 96D2-1G800NN-TRL1

Manufacturer:

Advantech

Description:

Memory Modules 1G DDR2-800 240PIN 128X8 VLP SAM(G)

Lifecycle:

New from this manufacturer.

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96D2-1G800NN-TRL1