T
T
T
S
S
S
2
2
2
Q
Q
Q
N
N
N
U
U
U
2
2
2
9
9
9
6
6
6
0
0
0
0
0
0
-
-
-
5
5
5
S
S
S
240PIN DDR2 800 Unbuffered DIMM 0.72”
1024MB With 128Mx8 CL6
Transcend Information Inc.
Timing Parameters & Specifications
(These AC characteristics were tested on the Component)
Parameter Symbol
Min Max Unit Note
DQ output access time from CK & /CK
tAC
-400 +400 ps
DQS output access time from CK & /CK tDQSCK
-350 +350 ps
CK high-level width
tCH 0.48 0.52 tCK
CK low-level width tCL 0.48 0.52 tCK
CK half period
tHP min(Tcl,tCH)
-
ps
Clock cycle time, CL=x
tCK 2500 8000 ps
DQ and DM input hold time
tDH 125 -
ps
DQ and DM input setup time
tDS 50 - ps
Control & Address input pulse width for each input
tIPW 0.6 - tCK
DQ and DM input pulse width for each input
tDIPW 0.35 - tCK
Data-out high-impedance time from CK/CK
tHZ -
tAC max
ps
DQS low-impedance time from CK/CK
tLZ(DQS)
tAC min tAC max ps
DQ low-impedance time from CK/CK
tLZ(DQ)
2* tACmin tACmax
ps
DQS-DQ skew for DQS and associated DQ signals
tDQSQ - 200 ps
DQ hold skew factor
tQHS - 300
ps
DQ/DQS output hold time from DQS
tQH tHP - tQHS - ps
Write command to first DQS latching transition
tDQSS -0.25 +0.25 tCK
DQS input high pulse width
tDQSH 0.35 - tCK
DQS input low pulse width
tDQSL 0.35 - tCK
DQS falling edge to CK setup time
tDSS
0.2 -
tCK
DQS falling edge hold time from CK
tDSH 0.2 - tCK
Mode register set command cycle time
tMRD 2 - tCK
Write postamble
tWPST 0.4 0.6 tCK
Write preamble
tWPRE 0.35 - tCK
Address and control input hold time
tIH 250 -
ps
Address and control input setup time
tIS 175 - ps
Read preamble
tRPRE 0.9 1.1 tCK
Read postamble
tRPST 0.4 0.6 tCK
Active to active command period for 1KB page size
products
tRRD 7.5 - ns
Active to active command period for 2KB page size
products
tRRD 10 - ns
Four Activate Window for 1KB page size products
tFAW 35 - ns