BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs
BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
(10) Random read cycle
BR24C01A-W / AF-W / AFJ-W / AFV-W
S
T
O
P
A
C
K
R
E
A
D
DATA(n)
SLAVE
ADDRESS
SLAVE
ADDRESS
WORD
ADDRESS(n)
SDA
LINE
S
T
A
R
T
S
T
A
R
T
110 0 A2 A1A0
R
/
W
R
/
W
A
C
K
A
C
K
A
C
K
W
R
I
T
E
110 0 A2 A1A0 D7 D0
Fig.13
WA
6
WA
0
BR24C02-W / F-W / FJ-W / FV-W
S
T
O
P
A
C
K
R
E
A
D
DATA(n)
SLAVE
ADDRESS
SLAVE
ADDRESS
WORD
ADDRESS(n)
SDA
LINE
S
T
A
R
T
S
T
A
R
T
110 0 A2 A1A0
R
/
W
R
/
W
A
C
K
A
C
K
A
C
K
W
R
I
T
E
110 0 A2A1 A0 D7 D0
Fig.14
WA
7
WA
0
BR24C04-W / F-W / FJ-W / FV-W
S
T
O
P
A
C
K
R
E
A
D
DATA(n)
SLAVE
ADDRESS
SLAVE
ADDRESS
WORD
ADDRESS(n)
SDA
LINE
S
T
A
R
T
S
T
A
R
T
110 0 A2 A1PS
R
/
W
R
/
W
A
C
K
A
C
K
A
C
K
WA
7
WA
0
W
R
I
T
E
110 0 A2A1PS D7 D0
Fig.15
This command can read the designated word address data.
When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next
word address data can be read. [All words all read enabled]
(See Fig.16 to 18 for the sequential read cycles.)
This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop
condition) by raising SCL to HIGH.
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs
BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
(11) Sequential read cycle (For a current read)
BR24C01A-W / AF-W / AFJ-W / AFV-W
S
T
A
R
T
SLAVE
ADDRESS
R
/
W
A
C
K
A
C
K
A
C
K
A
C
K
R
E
A
D
DATA(n)
DATA(n+x)
SDA
LINE
110 0 A2 A1A0 D7 D7D0 D0
S
T
O
P
Fig.16
BR24C02-W / F-W / FJ-W / FV-W
S
T
A
R
T
SLAVE
ADDRESS
R
/
W
A
C
K
A
C
K
A
C
K
A
C
K
R
E
A
D
DATA(n)
DATA(n+x)
SDA
LINE
110 0 A2 A1A0 D7 D7D0 D0
S
T
O
P
Fig.17
BR24C04-W / F-W / FJ-W / FV-W
S
T
A
R
T
SLAVE
ADDRESS
R
/
W
A
C
K
A
C
K
A
C
K
A
C
K
R
E
A
D
DATA(n)
DATA(n+x)
SDA
LINE
110 0 A2 A1PS D7 D7D0 D0
S
T
O
P
Fig.18
When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next
word address data can be read. [All words can be read]
This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop
condition) using the SCL signal HIGH.
Sequential reading can also be done with a random read.
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs
BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
!
!!
!Operation notes
(1) During power rise
During power rise, the V
CC
may rise passing though the low voltage domain in which the IC internal circuit does not
work. For this reason, there is a risk of misoperation when the power rises without full IC internal reset.
To prevent this, pay attention to the following points during a power rise.
1) Set SCL = SDA = “HIGH”
2) Raise the power so as to active the Power On Reset (P. O. R) circuit.
Follow the steps below as to operate the P. O. R. circuit properly.
1) Set the power rise time (tR) to within 10ms.
2) Set the OFF domain for once power has been cut to 100mS minimum.
V
CC
t
OFF
t
R
(2) SDA terminal pull-up resistance
The SDA terminal is an open drain output. Consequently, it requires an external pull-up resistance. The
appropriate pull-up resistance value is selected from the IC V
OL
-I
OL
features., which have been appended as
measuring data, as well as V
IL
and I
LI
and other personal icons that control the IC in question.
Recommended values 2.0k to 10kW
Fig.19 V
OL
I
OL
features (Note : Typ.)
2
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
01
Ta=25°C
345
Ta=85°C Ta=−40°C
V
CC
=3.0V V
CC
=5.0V V
CC
=3.0V
OUTPUT VOLTAGE : VOL (V)
V
CC
=3.0V V
CC
=5.0V V
CC
=5.0V
OUTPUT CURRENT : IOL (mA)
Note : All memory array data are set to “FF” status at time of shipping.

BR24C02FJ-WE2

Mfr. #:
Manufacturer:
Description:
EEPROM EEPROM
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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