BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs
BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
(9) Current read cycle
BR24C01A-W / AF-W / AFJ-W / AFV-W
SDA
LINE
S
T
A
R
T
SLAVE
ADDRESS
11
R
/
W
A
C
K
A
C
K
DATA
S
T
O
P
0 0 A2 A1 A0 D7 D0
R
E
A
D
Fig.10
BR24C02-W / F-W / FJ-W / FV-W
SDA
LINE
S
T
A
R
T
SLAVE
ADDRESS
11
R
/
W
A
C
K
A
C
K
DATA
S
T
O
P
0 0 A2 A1 A0 D7 D0
R
E
A
D
Fig.11
BR24C04-W / F-W / FJ-W / FV-W
SDA
LINE
S
T
A
R
T
SLAVE
ADDRESS
11
R
/
W
A
C
K
A
C
K
DATA
S
T
O
P
0 0 A2 A1 PS D7 D0
R
E
A
D
Fig.12
• In case the previous operation is random or current read (which includes sequential read respectively), the internal
address counter is increased by one from the last accessed address (n). Thus current read outputs the data of the
next word address (n+1).
If the last command is byte or page write, the internal address counter stays at the last address (n). Thus current
read outputs the data of the word address (n).
If the master does not transfer the acknowledge but does generate a stop condition, the current address read
operation only provides s single byte of data.
At this point, this IC discontinues transmission.
• When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next
word address data can be read. [All words all read enabled]
(See Fig.16 to 18 for the sequential read cycles.)
• This command is ended by inputting HIGH to the ACK signal after D0 and raising the SDA signal (stop condition) by
setting SCL to HIGH.
