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MC100EP17MNG

P1-P3P4-P6P7-P9P10-P11
© Semiconductor Components Industries, LLC, 2016
December, 2016 − Rev. 10
1 Publication Order Number:
MC10EP17/D
MC10EP17, MC100EP17
3.3V / 5V ECL Quad
Differential Driver/Receiver
Description
The MC10/100EP17 is a 4-bit differential line receiver based on the
EP17 device. The > 3.0 GHz maximum frequency provided by the
high frequency outputs makes the device ideal for buffering of very
high speed oscillators.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01ĂmF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
The design incorporates two stages of gain, internal to the device,
making it an excellent choice for use in high bandwidth amplifier
applications.
Inputs of unused gates can be left open and will not affect the
operation of the rest of the device. All V
CC
and V
EE
pins must be
externally connected to power supply to guarantee proper operation.
The 100 Series contains temperature compensation.
Features
• 220 ps Typical Propagation Delay
• Maximum Frequency > 3.0 GHz Typical
• PECL Mode Operating Range:
♦ V
CC
= 3.0 V to 5.5 V with V
EE
= 0 V
• NECL Mode Operating Range:
♦ V
CC
= 0 V with V
EE
= −3.0 V to −5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at V
EE
• V
BB
Output
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
XXXX = MC10 or 100
yyy = 10 or 100
A = Assembly Location
L, = Assembly Lot
WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb-Free Package
http://onsemi.com
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D
.
See detailed ordering and shipping information on page 8 o
f
this data sheet.
ORDERING INFORMATION
TSSOP−20
DT SUFFIX
CASE 948E
MARKING DIAGRAMS*
SOIC−20 WB
DW SUFFIX
CASE 751D−05
1
20
1
20
MCyyyEP17
AWLYYWWG
XXXX
EP17
ALYWG
G
1
20
QFN−20
MN SUFFIX
CASE 485E−0
1
XXXX
EP17
ALYWG
G
1
2
0
MC10EP17, MC100EP17
www.onsemi.com
2
D1
Figure 1. 20-Lead Pinout (Top View) and Logic Diagram
D1 D2 D3
1718 16 15 14 13 12
43
56789
Q0
11
10
Q1 Q1 Q2 Q2 Q3 Q3 V
EE
D0
1920
21
V
CC
Q0
D0 D2V
CC
D3 V
BB
PIN
D[0:3]*, D[0:3]
*
Q[0:3], Q[0:3]
ECL Differential Data Outputs
FUNCTION
ECL Differential Data Inputs
V
BB
V
CC
Positive Supply
Reference Voltage Output
V
EE
Negative Supply
Table 1. PIN DESCRIPTION
* Pins will default LOW when left open.
EP Exposed Pad
1
2
3
4
5
15
14
13
12
11
678910
20 19 18 17 16
Figure 1. QFN-20 Pinout (Top View)
Q0
Q1
Q1
V
CC
Q0V
CC
Q2
Q2
Q3
Q3
V
EE
D1
D1
D2
D0
D0
D2
D3 D3
V
BB
Exposed Pad
NOTE: The Exposed Pad (EP) on package bottom must be attached to a heat-sinking conduit.
The Exposed Pad may only be electrically connected to V
EE
.
MC10/100EP17
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg
SOIC−20 WB
TSSOP−20 WB
QFN−20
Level 3
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count 259 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MC10EP17, MC100EP17
www.onsemi.com
3
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
PECL Mode Power Supply V
EE
= 0 V 6 V
V
EE
NECL Mode Power Supply V
CC
= 0 V −6 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
v V
CC
V
I
w V
EE
6
−6
V
I
out
Output Current Continuous
Surge
50
100
mA
I
BB
V
BB
Sink/Source ± 0.5 mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
TSSOP−20 WB 140
100
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board TSSOP−20 WB 23 to 41 °C/W
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−20 WB 90
60
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board SOIC−20 WB 30 to 35 °C/W
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
QFN−20 47
33
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board QFN−20 18 °C/W
T
sol
Wave Solder (Pb-Free) 265 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 4. 10EP DC CHARACTERISTICS, PECL (V
CC
= 3.3 V, V
EE
= 0 V (Note 1))
Symbo
l
Characteristic
−40°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
I
EE
Power Supply Current 42 50 65 44 52 66 46 54 68 mA
V
OH
Output HIGH Voltage (Note 2) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV
V
OL
Output LOW Voltage (Note 2) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV
V
IH
Input HIGH Voltage (Single-Ended) 2090 2415 2155 2480 2215 2540 mV
V
IL
Input LOW Voltage (Single-Ended) 365 1690 1430 1755 1490 1815 mV
V
BB
Output Voltage Reference 1790 1890 1990 1855 1955 2055 1915 2015 2115 mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 3)
2.0 3.3 2.0 3.3 2.0 3.3 V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current 0.5 0.5 0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.3 V to −2.2 V.
2. All loading with 50 W to V
CC
− 2.0 V.
3. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
P1-P3P4-P6P7-P9P10-P11

MC100EP17MNG

Mfr. #:
Buy MC100EP17MNG
Manufacturer:
ON Semiconductor
Description:
Buffers & Line Drivers BBG ECL DIFRENTIAL
Lifecycle:
New from this manufacturer.
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