REV. A
AD8018
–9–
Table I. Resistor Selection Guide
Gain R
F
()R
G
()
1 681 681
+1 1 k
+2 750 750
+3 511 256
+4 340 113
+5 230 59
POWER-DOWN FEATURES
Two digitally programmable logic pins, PWDN1 and PWDN0,
are available on the TSSOP-14 package to select among three
different modes of operation, full power, standby and shutdown.
The DGND pin is the logic ground reference. The logic thresh-
old voltage is established 1 V above DGND. In a typical 5 V
single-supply application, the DGND pin is connected to analog
ground. If PWDN1, PWDN0, and DGND are left unconnected,
the AD8018 will operate at full power.
Table II. Power-Down Features and Truth Table
Supply Output
PWDN0 PWDN1 State Current Impedance
High High Full Power 18 mA Low
Low High Standby 9 mA Low
High Low Standby 9 mA Low
Low Low Disabled 300 µA High
POWER SUPPLY AND DECOUPLING
The AD8018 can be powered with a good quality (i.e., low-noise)
supply anywhere in the range from 3.3 V to 8 V. However, in
order to optimize the ADSL upstream drive capability to +13 dBm
and maintain the best Spurious Free Dynamic Range (SFDR),
the AD8018 circuit should be supplied with a well regulated 5 V
supply. The 5 V supplied at the Universal Serial Bus (USB) port
may be poorly regulated. Improving the quality of the 5 V supply
will optimize the performance of the AD8018 in a Universal Serial
Bus-supplied CPE ADSL modem. This can be accomplished
through the use of a step-up dc-to-dc converter or switching
power supply followed by a low dropout (LDO) regulator such
as the ADP3331 (see Figure 6). Setting R1 to be 953 k and
R2 to be 301 k will result in a V
OUT
of 5 V.
Careful attention must be paid to decoupling the power supply
pins at the output of the dc-to-dc converter, the output of the
LDO regulator and the supply pins of the AD8018. High-quality
capacitors with low equivalent series resistance (ESR) such as
multilayer ceramic capacitors (MLCCs) should be used to mini-
mize supply voltage ripple and power dissipation. A large, usually
tantalum, 10 µF to 47 µF capacitor located in proximity to the
AD8018 is required to provide good decoupling for lower fre-
quency signals. In addition, 0.1 µF MLCC decoupling capacitors
should be located as close to each of the power supply pins as is
physically possible, no more than 1/8 inch away. An additional
large (4.7 µF to 10 µF) tantalum capacitor should be placed on the
board near the supply terminals to supply current for fast, large-
signal changes at the AD8018 outputs.
ADP3331
C1
0.47F
V
IN
ON
OFF
V
OUT
E
OUT
C2
0.47F
R3
330k
IN
SD GND
OUT
FB
ERR
R1
953k
R2
301k
Figure 6. ADP3331 LDO
METHOD FOR GENERATING A MIDSUPPLY VOLTAGE
To operate an amplifier on a single voltage supply, a voltage
midway between the supply and ground must be generated to
properly bias the inputs and the outputs.
A voltage divider can be created with two equal value resistors
(Figure 7). There is a trade-off between the power consumed by
the divider and the voltage drop across these resistors due to the
positive input bias currents. Selecting 2.5 k for R1 and R2 will
create a voltage divider that draws only 1 mA from a 5 V supply.
The voltage generated with this topology can vary due to the
temperature coefficient (TC) of resistance. Resistors that are
closely matched and have a low TC will minimize variations in
the voltage reference due to temperature. One should also be
sure to use a decoupling capacitor (0.1 µF) at the node where
V
REF
is generated.
5V
R1
2.5k
R2
2.5k
V
REF
0.1F
Figure 7. Midsupply Reference
DIFFERENTIAL TESTING
The test circuit shown in TPC 13 is used for measuring the dif-
ferential distortion of the AD8018. A single-ended test signal is
applied to the inverting input of the AD8138 differential driver
with the noninverting input grounded. Applying the differential
output of the AD8138 through 100 resistors serves to isolate
the inputs of the AD8018 differential driver and provide a well-
balanced low-distortion input signal. The differential load (R
L
)
of the AD8018 can be set to the equivalent of the line imped-
ance reflected through a transformer. The AD9632 converts
the differential output voltage back to a single-ended signal.
The differential-to- single-ended converter using the AD9632
has an attenuation of 26 dB and is wired with precision resis-
tors to optimize the balance of differential input signal. The
resulting smaller output signal can be easily measured using a
50 spectrum analyzer.
REV. A
AD8018
–10–
P V rmsV V rms
R
IV P
TOT O S O
L
Q S OUT
++408
1
2
2
(. ) α
For the AD8018, operating on a single 5 V supply and deliver-
ing a total of 16 dBm (13 dBm to the line and 3 dBm to the
matching network) into 12.5 (100 reflected back through
a 1:4.0 transformer plus back termination), the power is:
= 261 mW + 40 mW
= 301 mW
Using these calculations, and a θ
JA
of 115°C/W for the TSSOP
package and 100°C/W for the SOIC, Tables III and IV show
junction temperature versus power delivered to the line for sev-
eral supply voltages.
Table III. Junction Temperature vs. Line Power and
Operating Voltage for TSSOP, T
AMB
= 85C
V
SUPPLY
P
LINE,
dBm 5 6 7 8
13 115 122 129 136
14 117 125 132 140
15 119 127 136 144
16 121 130 139 148
17 123 133 143 153
18 125 136 147 158
Table IV. Junction Temperature vs. Line Power and
Operating Voltage for SOIC, T
AMB
= 85C
V
SUPPLY
P
LINE,
dBm 5 6 7 8
13 111 117 123 129
14 113 119 126 133
15 115 122 129 136
16 116 124 132 140
17 118 127 136 144
18 120 130 139 149
Running the AD8018 at voltages near 8 V can produce junction
temperatures that exceed the thermal rating of the TSSOP pack-
ages and should be avoided. The shaded areas indicate junction
temperatures greater than 150°C.
LAYOUT CONSIDERATIONS
As is the case with all high-speed applications, careful attention
to printed circuit board layout details will prevent associated
board parasitics from becoming problematic. Proper RF design
technique is mandatory. The PCB should have a ground plane
covering all unused portions of the component side of the board
to provide a low-impedance return path. Removing the ground
plane on all layers from the area near the input and output pins
will reduce stray capacitance, particularly in the area of the
inverting inputs. Signal lines connecting the feedback and gain
resistors should be as short as possible to minimize the inductance
and stray capacitance associated with these traces. Termination
resistors and loads should be located as close as possible to their
respective inputs and outputs. Input and output traces should
be kept as far apart as possible to minimize coupling (crosstalk)
though the board. Adherence to stripline design techniques for
long signal traces (greater than about 1 inch) is recommended.
This circuit requires significant power supply bypassing. The
AD8018 operates on a split supply in this circuit. The bypassing
technique shown in TPC 13 utilizes a 220 µF tantalum capacitor
and a 0.1 µF ceramic chip capacitor in parallel, connected from
the positive to negative supply, and a 10 µF tantalum and 0.1 µF
ceramic chip capacitor in parallel, connected from each supply to
ground. The capacitors connected between the power supplies
serve to minimize any voltage ripples that might appear at the
supplies while sourcing or sinking any large differential current.
The large capacitor has a pool of charge instantly available for
the AD8018 to draw from, thus preventing any erroneous dis-
tortion results.
POWER DISSIPATION
It is important to consider the total power dissipation of the
AD8018 in order to properly size the heat sink area of an
application. Figure 8 is a simple representation of a differential
driver. With some simplifying assumptions we can estimate the
total power dissipated in this circuit. If the output current is
large compared to the quiescent current, computing the dissipa-
tion in the output devices and adding it to the quiescent power
dissipation will give a close approximation of the total power
dissipation in the package. A factor α (~0.6-1) corrects for the
slight error due to the Class A/B operation of the output stage.
It can be estimated by subtracting the quiescent current in the
output stage from the total quiescent current and ratioing that
to the total quiescent current. For the AD8018, α = 0.833.
+V
S
V
S
+V
O
+V
S
V
S
V
O
R
L
Figure 8. Simplified Differential Driver
Remembering that each output device dissipates for only half
the time gives a simple integral that computes the power for
each device:
1
2
2
×
( )VV
V
R
SO
O
L
The total supply power can then be computed as:
PVVV
R
IV P
TOT S O O
L
Q S OUT
=
×+ +4
1
2
2
|| α
In this differential driver, V
O
is the voltage at the output of one
amplifier, so 2 V
O
is the voltage across R
L,
which is the total
impedance seen by the differential driver, including back termina-
tion. Now, with two observations, the integrals are easily evaluated.
First, the integral of V
O
2
is simply the square of the rms value of
V
O
. Second, the integral of |V
O
| is equal to the average recti-
fied value of V
O
, sometimes called the Mean Average Deviation, or
MAD. It can be shown that for a Discrete MultiTone (DMT)
signal, the MAD value is equal to 0.8 times the rms value.
REV. A
AD8018
–11–
Following these generic guidelines will improve the performance
of the AD8018 in all applications.
To optimize the AD8018s performance as an ADSL differential
line driver, locate the transformer hybrid near the AD8018 drivers
and as close to the RJ11 jack as possible. Maintain differential
circuit symmetry into the differential driver and from the output
of the drivers through the transformer-coupled output of the bridge
circuit as much as possible.
CPE ADSL Application
The low-cost, high-output current dual AD8018 xDSL driver
amplifiers have been specifically designed to drive high fidelity
xDSL signals to within 0.5 V of the power rails, the performance
needed to provide CPE ADSL on a single 5 V supply. The
AD8018 may be used in transformer-coupled bridge hybrid cir-
cuits to drive modulated signals including Discrete MultiTone
(DMT) upstream to the central office.
Evaluation Board
The AD8018ARU-EVAL evaluation board circuit in Figure 12
offers the ability to evaluate the AD8018 in a typical xDSL bridge
hybrid circuit.
The receiver circuit on these boards is typically unpopulated.
Requesting samples of the AD8022AR with the AD8018ARU-
EVAL board will provide the capability to evaluate the
AD8018ARU along with other Analog Devices products in a typi-
cal transceiver circuit. The evaluation circuits have been designed
to replicate the CPE side analog transceiver hybrid circuits.
The circuit mentioned above is designed using a one-transformer
transceiver topology including a line receiver, line driver, line
matching network, an RJ11 jack for interfacing to line simulators,
and transformer-coupled inputs for single-ended-to-differential
input conversion.
AC-coupling capacitors of 0.01 µF, C8, and C10, in combina-
tion with 10 k resistors R24 and R25, will form a zero frequency
at 1.6 kHz.
Transformer Selection
Customer premise ADSL requires the transmission of a +13 dBm
(20 mW) DMT signal. The DMT signal can have a crest factor
as high as 5.3, requiring the line driver to provide peak line power
of 27.5 dBm (560 mW). 27.5 dBm peak line power translates
into a 7.5 V peak voltage on the 100 telephone line. Assuming
that the maximum low-distortion output swing available from
the AD8018 line driver on a 5 V supply is 4 V and, taking into
account the power lost due to the termination resistance, a step-up
transformer with turns ratio of 4.0 or greater is needed.
In the simplified differential drive circuit shown in Figure 2, the
AD8018 is coupled to the phone line through a step-up trans-
former with a 1:4 turns ratio. R1 and R2 are back-termination
or line-matching resistors, each 3.1 (100 /(2 × 4
2
)), where
100 is the approximate phone line impedance. The total dif-
ferential load for the AD8018, including the termination resistors,
is 12.5 . Even under these conditions the AD8018 provides low
distortion signals to within 0.5 V of the power rails.
Stability Enhancements
The CPE bridge hybrid circuit presents a complex impedance to
the drive amplifiers, particularly when transformer parasitics are
factored in. To ensure stable operation under the full range of
load conditions, a series R-C network (Zoebel Network) should
be connected between each amplifiers output and ground. The
recommended values are 10 for the resistor and 1 nF for the
capacitor to create a low impedance path to ground at frequen-
cies above 16 MHz (see Figure 2). R33 and R34 are added to
improve common-mode stability.
Receive Channel Considerations
A transformer used at the output of the differential line driver to
step up the differential output voltage to the line has the inverse
effect on signals received from the line. A voltage reduction
or attenuation equal to the inverse of the turns ratio is realized
in the receive channel of a typical bridge hybrid. The turns ratio
of the transformer may also be dictated by the ability of the receive
circuitry to resolve low-level signals in the noisy twisted pair tele-
phone plant. Higher turns ratio transformers effectively reduce the
received signal-to-noise ratio due to the reduction in the received
signal strength.
The AD8022, a dual amplifier with typical RTI voltage noise of
only 2.5 nV/Hz and a low supply current of 4 mA/amplifier, is
recommended for the receive channel.
DMT Modulation, MultiTone Power Ratio (MTPR), and
Out-of-Band SFDR
ADSL systems rely on DMT modulation to carry digital data
over phone lines. DMT modulation appears in the frequency
domain as power contained in several individual frequency
subbands, sometimes referred to as tones or bins, each of which
is uniformly separated in frequency. A uniquely encoded, Quadra-
ture Amplitude Modulation (QAM)-like signal occurs at the center
frequency of each subband or tone. See Figure 9 for an example
of a DMT waveform in the frequency domain, and Figure 10 for
a time domain waveform. Difficulties will exist when decoding
these subbands if a QAM signal from one subband is corrupted
by the QAM signal(s) from other subbands, regardless of whether
the corruption comes from an adjacent subband or harmonics of
other subbands.
Conventional methods of expressing the output signal integrity
of line drivers, such as single-tone harmonic distortion or THD,
two-tone InterModulation Distortion (IMD), and third order
intercept (IP3), become significantly less meaningful when
amplifiers are required to process DMT and other heavily
modulated waveforms. A typical ADSL upstream DMT signal
can contain as many as 27 carriers (subbands or tones) of
QAM signals. MultiTone Power Ratio (MTPR) is the relative
difference between the measured power in a typical subband (at
one tone or carrier) versus the power at another subband spe-
cifically selected to contain no QAM data. In other words, a
selected subband (or tone) remains open or void of intentional
power (without a QAM signal), yielding an empty frequency bin.
MTPR, sometimes referred to as the empty bin test, is
typically expressed in dBc, similar to expressing the relative
difference between single-tone fundamentals and second or
third harmonic distortion components. Measurements of MTPR
are typically made on the line side or secondary side of the
transformer.

AD8018AR-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Special Purpose Amplifiers 5V RRO Crnt xDSL Line Dvr
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