1. General description
The 74ABT823 high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT823 is a 9-bit wide buffered register with clock enable input (CE
) and master
reset input (MR
) which are ideal for parity bus interfacing in systems using many
microprocessors.
The 74ABT823 is designed to eliminate the extra packages required to buffer existing
registers and provide extra data width for wider data and address paths of buses carrying
parity.
The register is fully edge-triggered. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the corresponding output Q of the flip-flop.
2. Features and benefits
High-speed parallel registers with positive edge-triggered D-type flip-flops
Ideal where high speed, light loading, or increased fan-in are required with MOS
microprocessors
Output capability: +64 mA and 32 mA
Power-on 3-state
Power-on reset
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
3. Ordering information
74ABT823
9-bit D-type flip-flop with reset and enable; 3-state
Rev. 4 — 7 November 2011 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74ABT823D 40 C to +85 C SO24 plastic small outline package; 24 leads;
body width 7.5 mm
SOT137-1
74ABT823DB 40 C to +85 C SSOP24 plastic shrink small outline package; 24 leads;
body width 5.3 mm
SOT340-1
74ABT823PW 40 C to +85 C TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
