74ABT823 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 7 November 2011 7 of 17
NXP Semiconductors
74ABT823
9-bit D-type flip-flop with reset and enable; 3-state
[1] For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
[2] This parameter is valid for any V
CC
between 0 V and 2.1 V, with a transition time of up to 10 ms. From V
CC
= 2.1 V to V
CC
= 5 V 10 %
a transition time of up to 100 s is permitted.
[3] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
[4] This is the increase in supply current for each input at 3.4 V.
10. Dynamic characteristics
I
CC
additional supply
current
per input pin; V
CC
= 5.5 V;
one input at 3.4 V;
other inputs at V
CC
or GND
[4]
-0.51.5 - 1.5mA
C
I
input capacitance V
I
=0Vor V
CC
-4- - -pF
C
O
output capacitance outputs disabled; V
O
=0Vor V
CC
-7- - -pF
Table 6. Static characteristics …continued
Symbol Parameter Conditions 25 C 40 C to +85 C Unit
Min Typ Max Min Max
Table 7. Dynamic characteristics
GND = 0 V; for test circuit, see Figure 9.
Symbol Parameter Conditions 25 C; V
CC
= 5.0 V 40 C to +85 C;
V
CC
= 5.0 V 0.5 V
Unit
Min Typ Max Min Max
f
max
maximum
frequency
see Figure 5 125 200 - 125 - MHz
t
PLH
LOW to HIGH
propagation delay
CP to Qn, see Figure 5 2.1 4.3 5.9 2.1 6.8 ns
t
PHL
HIGH to LOW
propagation delay
CP to Qn, see Figure 5 2.2 4.4 6.1 2.2 6.7 ns
MR
to Qn, see Figure 6 2.0 4.1 6.3 2.0 7.1 ns
t
PZH
OFF-state to HIGH
propagation delay
OE to Qn; see Figure 8 1.0 3.0 4.5 1.0 5.3 ns
t
PZL
OFF-state to LOW
propagation delay
OE to Qn; see Figure 8 2.2 4.1 5.6 2.2 6.3 ns
t
PHZ
HIGH to OFF-state
propagation delay
OE to Qn; see Figure 8 2.7 4.8 6.2 2.7 6.9 ns
t
PLZ
LOW to OFF-state
propagation delay
OE to Qn; see Figure 8 2.5 5.0 6.4 2.5 6.9 ns
t
su(H)
set-up time HIGH Dn to CP; see Figure 7 2.1 0.5 - 2.1 - ns
CE
to CP; see Figure 7 +2.0 0.5 - +2.0 - ns
t
su(L)
set-up time LOW Dn to CP; see Figure 7 2.1 0.2 - 2.1 - ns
CE
to CP; see Figure 7 3.3 1.5 - 3.3 - ns
t
h(H)
hold time HIGH CP to Dn; see Figure 7 1.3 0.0 - 1.3 - ns
CP to CE
; see Figure 7 +1.0 1.4 - +1.0 - ns
t
h(L)
hold time LOW CP to Dn; see Figure 7 +1.3 0.3 - +1.3 - ns
CP to CE
; see Figure 7 2.0 0.7 - 2.0 - ns
t
WH
pulse width HIGH CP; see Figure 5 2.9 1.9 - 2.9 - ns
