PCA9632 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 27 July 2011 15 of 39
NXP Semiconductors
PCA9632
4-bit Fm+ I
2
C-bus low power LED driver
Once subaddresses have been programmed to their right values, SUBx bits need to be
set to 1 in order to have the device acknowledging these addresses (MODE1 register).
Only the 7 MSBs representing the I
2
C-bus subaddress are valid. The LSB in SUBADRx
register is a read-only bit (0).
When SUBx is set to 1, the corresponding I
2
C-bus subaddress can be used during either
an I
2
C-bus read or write sequence.
7.3.8 LED All Call I
2
C-bus address, ALLCALLADR
The LED All Call I
2
C-bus address allows all the PCA9632s in the bus to be programmed
at the same time (ALLCALL bit in register MODE1 must be equal to 1, power-up default
state). This address is programmable through the I
2
C-bus and can be used during either
an I
2
C-bus read or write sequence. The register address can be programmed as a
sub call.
Only the 7 MSBs representing the All Call I
2
C-bus address are valid. The LSB in
ALLCALLADR register is a read-only bit (0).
If ALLCALL bit = 0, the device does not acknowledge the address programmed in register
ALLCALLADR.
7.4 Power-on reset
When power is applied to V
DD
, an internal power-on reset holds the PCA9632 in a reset
condition until V
DD
has reached V
POR
. At this point, the reset condition is released and the
PCA9632 registers and I
2
C-bus state machine are initialized to their default states (all
zeroes) causing all the channels to be deselected. Thereafter, V
DD
must be lowered below
0.2 V to reset the device.
7.5 Software reset
The Software Reset Call (SWRST Call) allows all the devices in the I
2
C-bus to be reset to
the power-up state value through a specific formatted I
2
C-bus command. To be performed
correctly, it implies that the I
2
C-bus is functional and that there is no device hanging the
bus.
The SWRST Call function is defined as the following:
1. A START command is sent by the I
2
C-bus master.
2. The reserved SWRST I
2
C-bus address ‘0000 011’ with the R/W bit set to 0 (write) is
sent by the I
2
C-bus master.
3. The PCA9632 device(s) acknowledge(s) after seeing the SWRST Call address
‘0000 0110’ (06h) only. If the R/W
bit is set to 1 (read), no acknowledge is returned to
the I
2
C-bus master.
Table 13. ALLCALLADR - LED All Call I
2
C-bus address register (address 0Ch) bit
description
Legend: * default value.
Address Register Bit Symbol Access Value Description
0Ch ALLCALLADR 7:1 AC[7:1] R/W 1110 000* ALLCALL I
2
C-bus
address register
0 AC[0] R only 0* reserved
