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LTC3407EDD-3#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
LTC3407-3
10
34073fb
APPLICATIONS INFORMATION
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfi ll a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation and
the output capacitor size. Typically, 3-4 cycles are required
to respond to a load step, but only in the fi rst cycle does
the output drop linearly. The output droop, V
DROOP
, is
usually about 2-3 times the linear drop of the fi rst cycle.
Thus, a good place to start is with the output capacitor
size of approximately:
C
OUT
≈ 2.5
ΔI
OUT
f
O
•V
DROOP
More capacitance may be required depending on the duty
cycle and load step requirements.
In most applications, the input capacitor is merely required
to supply high frequency bypassing, since the impedance
to the supply is very low. A 10μF ceramic capacitor is
usually enough for these conditions.
Power-On Reset
The POR pin is an open-drain output which pulls low when
either regulator is out of regulation. When both output volt-
ages are above –8.5% of regulation, a timer is started which
releases POR after 2
18
clock cycles (about 117ms). This
delay can be signifi cantly longer in Burst Mode operation
with low load currents, since the clock cycles only occur
during a burst and there could be milliseconds of time
between bursts. This can be bypassed by tying the POR
output to the MODE/SYNC input, to force pulse-skipping
mode during a reset. In addition, if the output voltage
faults during Burst Mode sleep, POR could have a slight
delay for an undervoltage output condition and may not
respond to an overvoltage output. This can be avoided by
using pulse-skipping mode instead. When either channel
is shut down, the POR output is pulled low, since one or
both of the channels are not in regulation.
Mode Selection & Frequency Synchronization
The MODE/SYNC pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connect-
ing this pin to V
IN
enables Burst Mode operation, which
provides the best low current effi ciency at the cost of a
higher output voltage ripple. Connecting this pin to ground
selects pulse-skipping mode, which provides the lowest
output ripple, at the cost of low current effi ciency.
The LTC3407-3 can also be synchronized to an external
2.25MHz clock signal (such as the SW pin on another
LTC3407-3) by the MODE/SYNC pin. During synchro-
nization, the mode is set to pulse-skipping and the top
switch turn-on is synchronized to the rising edge of the
external clock.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to ΔI
LOAD
• ESR, where ESR is the effective series
resistance of C
OUT
. ΔI
LOAD
also begins to charge or dis-
charge C
OUT
, generating a feedback error signal used by the
regulator to return V
OUT
to its steady-state value. During
this recovery time, V
OUT
can be monitored for overshoot or
ringing that would indicate a stability problem. The initial
output voltage step may not be within the bandwidth of the
feedback loop, so the standard second-order overshoot/DC
ratio cannot be used to determine phase margin.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a re-
view of control loop theory, refer to Application Note 76.
In some applications, a more severe transient can be caused
by switching in loads with large (>1μF) input capacitors.
The discharged input capacitors are effectively put in paral-
lel with C
OUT
, causing a rapid drop in V
OUT
. No regulator
can deliver enough current to prevent this problem, if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot Swap™ controller is designed
specifi cally for this purpose and usually incorporates cur-
rent limiting, short-circuit protection, and soft-starting.
Hot Swap is a trademark of Linear Technology Corporation.
LTC3407-3
11
34073fb
APPLICATIONS INFORMATION
Effi ciency Considerations
The percent effi ciency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the effi ciency and which change would
produce the most improvement. Percent effi ciency can
be expressed as:
%Effi ciency = 100% - (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, 4 main sources usually account for most of the
losses in LTC3407-3 circuits: 1)V
IN
quiescent current, 2)
switching losses, 3) I
2
R losses, 4) other losses.
1) The V
IN
current is the DC supply current given in the
Electrical Characteristics which excludes MOSFET driver
and control currents. V
IN
current results in a small (<0.1%)
loss that increases with V
IN
, even at no load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
from switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high
to low again, a packet of charge dQ moves from V
IN
to
ground. The resulting dQ/dt is a current out of V
IN
that is
typically much larger than the DC bias current. In continu-
ous mode, I
GATECHG
= f
O
(Q
T
+ Q
B
), where Q
T
and Q
B
are
the gate charges of the internal top and bottom MOSFET
switches. The gate charge losses are proportional to V
IN
and thus their effects will be more pronounced at higher
supply voltages.
3) I
2
R losses are calculated from the DC resistances of
the internal switches, R
SW
, and external inductor, R
L
. In
continuous mode, the average output current fl ows through
inductor L, but is “chopped” between the internal top and
bottom switches. Thus, the series resistance looking into
the SW pin is a function of both top and bottom MOSFET
R
DS(ON)
and the duty cycle (DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
2
R losses:
I
2
R losses = I
OUT
2
(R
SW
+ R
L
)
4) Other ‘hidden’ losses such as copper trace and internal
battery resistances can account for additional effi ciency
degradations in portable systems. It is very important
to include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that C
IN
has adequate
charge storage and very low ESR at the switching frequency.
Other losses including diode conduction losses during
dead-time and inductor core losses generally account for
less than 2% total additional loss.
Thermal Considerations
In a majority of applications, the LTC3407-3 does not
dissipate much heat due to its high effi ciency. However,
in applications where the LTC3407-3 is running at high
ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will turn off and the SW node will
become high impedance.
To prevent the LTC3407-3 from exceeding the maximum
junction temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
T
RISE
= P
D
• θ
JA
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
RISE
+ T
AMBIENT
As an example, consider the case when the LTC3407-3 is
in dropout on both channels at an input voltage of 2.7V
LTC3407-3
12
34073fb
APPLICATIONS INFORMATION
with a load current of 800mA and an ambient temperature
of 70°C. From the Typical Performance Characteristics
graph of Switch Resistance, the R
DS(ON)
resistance of
the main switch is 0.425Ω. Therefore, power dissipated
by each channel is:
P
D
= I
OUT
2
• R
DS(ON)
= 272mW
The DFN package junction-to-ambient thermal resistance,
θ
JA
, is 40°C/W. Therefore, the junction temperature of
the regulator operating in a 70°C ambient temperature is
approximately:
T
J
= 2 • 0.272 • 40 + 70 = 91.8°C
which is below the absolute maximum junction tempera-
ture of 125°C.
Design Example
As a design example, consider using the LTC3407-3 in
an portable application with a Li-Ion battery. The battery
provides a V
IN
= 2.8V to 4.2V. The load requires a maximum
of 800mA in active mode and 2mA in standby mode. The
output voltage is V
OUT
= 1.8V. Since the load still needs
power in standby, Burst Mode operation is selected for
good low load effi ciency.
First, calculate the inductor value for about 30% ripple
current at maximum V
IN
:
L
1.8V
2.25MHz • 300m
A
•1–
1.8V
4.2V
=1.5μH
Choosing a vendor’s closest inductor value of 2.2μH,
results in a maximum ripple current of:
I
L
=
1.8V
2.25MHz • 2.2μ
H
•1
1.8V
4.2V
= 208mA
For cost reasons, a ceramic capacitor will be used. C
OUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
A good standard value is 10μF. Since the output impedance
of a Li-Ion battery is very low, C
IN
is typically 10μF.
The POR pin is a common drain output and requires a pull-
up resistor. A 100k resistor is used for adequate speed.
Figure 1 shows the complete schematic for this design
example.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3407-3. These items are also illustrated graphically
in the layout diagram of Figure 3. Check the following in
your layout:
1. Does the capacitor C
IN
connect to the power V
IN
(Pin
3) and GND (exposed pad) as close as possible? This
capacitor provides the AC current to the internal power
MOSFETs and their drivers.
Figure 3. LTC3407-3 Layout Diagram (See Board Layout Checklist)
RUN2 V
IN
V
IN
V
OUT2
V
OUT1
RUN1
POR
SW1
V
FB1
GND
V
FB2
SW2
MODE/SYNC
LTC3407-3
C
IN
L1
L2
C
OUT2
C
OUT1
34073 F03
BOLD LINES INDICATE
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LTC3407EDD-3#PBF

Mfr. #:
Buy LTC3407EDD-3#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual, Sync. 800mA 2.25MHz Step-dwn Converter in DFN
Lifecycle:
New from this manufacturer.
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