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LTC3407EDD-3#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
LTC3407-3
7
34073fb
OPERATION
The LTC3407-3 uses a constant frequency, current mode
architecture. The operating frequency is set at 2.25MHz
and can be synchronized to an external oscillator. Both
channels share the same clock and run in-phase. To suit
a variety of applications, the selectable Mode pin allows
the user to choose between low noise and light load ef-
fi ciency.
The output voltage is set by an internal divider. An error
amplifi er compares the divided output voltage with a
reference voltage of 0.6V and adjusts the peak inductor
current accordingly. An undervoltage comparator pulls the
POR output low if the output voltage is not above –8.5%
of the reference voltage. The POR output will go high after
262,144 clock cycles of achieving regulation.
Main Control Loop
During normal operation, the top power switch (P-channel
MOSFET) is turned on at the beginning of a clock cycle
when the V
OUT
voltage is below the the regulated voltage.
The current fl ows into the inductor and the load increases
until the current limit is reached. The switch turns off and
energy stored in the inductor fl ows through the bottom
switch (N-channel MOSFET) into the load until the next
clock cycle.
The peak inductor current is controlled by the internally
compensated I
TH
voltage, which is the output of the er-
ror amplifi er. This amplifi er compares the V
FB
(see Block
Diagram) to the 0.6V reference. When the load current
increases, the V
FB
voltage decreases slightly below the
reference. This decrease causes the error amplifi er to
increase the I
TH
voltage until the average inductor current
matches the new load current.
The main control loop is shut down by pulling the RUN
pin to ground.
Low Current Operation
Two modes are available to control the operation of the
LTC3407-3 at low currents. Both modes automatically
switch from continuous operation to the selected mode
when the load current is low.
To optimize effi ciency, the Burst Mode operation can be
selected. When the load is relatively light, the LTC3407-3
automatically switches into Burst Mode operation, in which
the PMOS switch operates intermittently based on load
demand with a fi xed peak inductor current. By running
cycles periodically, the switching losses which are domi-
nated by the gate charge losses of the power MOSFETs
are minimized. The main control loop is interrupted when
the output voltage reaches the desired regulated value. A
voltage comparator trips when I
TH
is below 0.65V, shutting
off the switch and reducing the power. The output capaci-
tor and the inductor supply the power to the load until I
TH
exceeds 0.65V, turning on the switch and the main control
loop which starts another cycle.
For lower ripple noise at low currents, the pulse-skipping
mode can be used. In this mode, the LTC3407-3 continues
to switch at a constant frequency down to very low cur-
rents, where it will begin skipping pulses. The effi ciency in
pulse-skipping mode can be improved slightly by connect-
ing the SW node to the MODE/SYNC input which reduces
the clock frequency by approximately 30%.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which
is the dropout condition. In dropout, the PMOS switch is
turned on continuously with the output voltage being equal
to the input voltage minus the voltage drops across the
internal P-channel MOSFET and the inductor.
An important design consideration is that the R
DS(ON)
of the P-channel switch increases with decreasing input
supply voltage (See Typical Performance Characteristics).
Therefore, the user should calculate the power dissipation
when the LTC3407-3 is used at 100% duty cycle with low
input voltage (See Thermal Considerations in the Applica-
tions Information Section).
Low Supply Operation
To prevent unstable operation, the LTC3407-3 incorporates
an undervoltage lockout circuit which shuts down the part
when the input voltage drops below about 1.65V.
LTC3407-3
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34073fb
A general LTC3407-3 application circuit is shown in
Figure 2. External component selection is driven by the
load requirement, and begins with the selection of the
inductor L. Once the inductor is chosen, C
IN
and C
OUT
can be selected.
Inductor Selection
Although the inductor does not infl uence the operat-
ing frequency, the inductor value has a direct effect on
ripple current. The inductor ripple current ΔI
L
decreases
with higher inductance and increases with higher V
IN
or
V
OUT
:
I
L
=
V
OUT
f
O
•L
•1–
V
OUT
V
IN
Accepting larger values of ΔI
L
allows the use of low
inductances, but results in higher output voltage ripple,
greater core losses, and lower output current capability. A
reasonable starting point for setting ripple current is ΔI
L
=
0.3 • I
LIM
, where I
LIM
is the peak switch current limit. The
largest ripple current ΔI
L
occurs at the maximum input
voltage. To guarantee that the ripple current stays below a
specifi ed maximum, the inductor value should be chosen
according to the following equation:
L
V
OUT
f
O
• I
L
•1–
V
OUT
V
IN(MAX)
The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation
begins when the peak inductor current falls below a level
set by the burst clamp. Lower inductor values result in
higher ripple current which causes this to occur at lower
load currents. This causes a dip in effi ciency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency
to increase.
Inductor Core Selection
Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar elec-
trical characteristics. The choice of which style inductor
to use often depends more on the price vs size require-
ments and any radiated fi eld/EMI requirements than on
APPLICATIONS INFORMATION
what the LTC3407-3 requires to operate. Table 1 shows
some typical surface mount inductors that work well in
LTC3407-3 applications.
Table 1. Representative Surface Mount Inductors
PART
NUMBER
VALUE
(μH)
DCR
(Ω MAX)
MAX DC
CURRENT (A)
SIZE
W × L × H (mm
3
)
Sumida
CDRH3D16
2.2
3.3
4.7
0.075
0.110
0.162
1.20
1.10
0.90
3.8 × 3.8 × 1.8
Sumida
CDRH2D11
1.5
2.2
0.068
0.170
0.900
0.780
3.2 × 3.2 × 1.2
Sumida
CMD4D11
2.2
3.3
0.116
0.174
0.950
0.770
4.4 × 5.8 × 1.2
Murata
LQH32CN
1.0
2.2
0.060
0.097
1.00
0.79
2.5 × 3.2 × 2.0
Toko
D312F
2.2
3.3
0.060
0.260
1.08
0.92
2.5 × 3.2 × 2.0
Panasonic
ELT5KT
3.3
4.7
0.17
0.20
1.00
0.95
4.5 × 5.4 × 1.2
Input Capacitor (C
IN
) Selection
In continuous mode, the input current of the converter is a
square wave with a duty cycle of approximately V
OUT
/V
IN
.
To prevent large voltage transients, a low equivalent series
resistance (ESR) input capacitor sized for the maximum
RMS current must be used. The maximum RMS capacitor
current is given by:
I
RMS
≈I
MAX
V
OUT
(V
IN
–V
OUT
)
V
IN
where the maximum average output current I
MAX
equals
the peak current minus half the peak-to-peak ripple cur-
rent, I
MAX
= I
LIM
– ΔI
L
/2.
This formula has a maximum at V
IN
= 2V
OUT
, where I
RMS
= I
OUT
/2. This simple worst-case is commonly used to
design because even signifi cant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple cur-
rent ratings are often based on only 2000 hours lifetime.
This makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to meet
the size or height requirements of the design. An additional
0.1μF to 1μF ceramic capacitor is also recommended on
V
IN
for high frequency decoupling, when not using an all
ceramic capacitor solution.
LTC3407-3
9
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APPLICATIONS INFORMATION
Output Capacitor (C
OUT
) Selection
The selection of C
OUT
is driven by the required ESR to
minimize voltage ripple and load step transients. Typically,
once the ESR requirement is satisfi ed, the capacitance
is adequate for fi ltering. The output ripple (ΔV
OUT
) is
determined by:
V
OUT
I
L
ESR+
1
8f
O
C
OUT
where f = operating frequency, C
OUT
= output capacitance
and ΔI
L
= ripple current in the inductor. The output ripple
is highest at maximum input voltage since ΔI
L
increases
with input voltage. With ΔI
L
= 0.3 • I
LIM
the output ripple
will be less than 100mV at maximum V
IN
and f
O
= 2.25MHz
with:
ESR
COUT
< 150mΩ
Once the ESR requirements for C
OUT
have been met, the
RMS current rating generally far exceeds the I
RIPPLE(P-P)
requirement, except for an all ceramic solution.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or
RMS current handling requirement of the application.
Aluminum electrolytic, special polymer, ceramic and dry
tantulum capacitors are all available in surface mount
packages. The OS-CON semiconductor dielectric capacitor
available from Sanyo has the lowest ESR(size) product
of any aluminum electrolytic at a somewhat higher price.
Special polymer capacitors, such as Sanyo POSCAP,
Panasonic Special Polymer (SP), and Kemet A700, of-
fer very low ESR, but have a lower capacitance density
than other types. Tantalum capacitors have the highest
capacitance density, but they have a larger ESR and it
is critical that the capacitors are surge tested for use in
switching power supplies. An excellent choice is the AVX
TPS series of surface mount tantalums, available in case
heights ranging from 2mm to 4mm. Aluminum electrolytic
capacitors have a signifi cantly larger ESR, and are often
used in extremely cost-sensitive applications provided that
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have the lowest ESR
and cost, but also have the lowest capacitance density,
a high voltage and temperature coeffi cient, and exhibit
audible piezoelectric effects. In addition, the high Q of
ceramic capacitors along with trace inductance can lead
to signifi cant ringing.
In most cases, 0.1μF to 1μF of ceramic capacitors should
also be placed close to the LTC3407-3 in parallel with the
main capacitors for high frequency decoupling.
Figure 2. LTC3407-3 General Schematic
RUN2 V
IN
V
IN
V
OUT2
V
OUT1
RUN1
POR
SW1
V
OUT1
GND
V
OUT2
SW2
MODE/SYNC
LTC3407-3
10μF
100k
RESET
L1 μH
L2 μH
C
OUT2
C
OUT1
34073 F02
Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now be-
coming available in smaller case sizes. These are tempting
for switching regulator use because of their very low ESR.
Unfortunately, the ESR is so low that it can cause loop
stability problems. Solid tantalum capacitor ESR generates
a loop “zero” at 5kHz to 50kHz that is instrumental in giving
acceptable loop phase margin. Ceramic capacitors remain
capacitive to beyond 300kHz and usually resonate with their
ESL before ESR becomes effective. Also, ceramic caps are
prone to temperature effects which requires the designer
to check loop stability over the operating temperature
range. To minimize their large temperature and voltage
coeffi cients, only X5R or X7R ceramic capacitors should
be used. A good selection of ceramic capacitors is available
from Taiyo Yuden, AVX, Kemet, TDK, and Murata.
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, such as from a wall adapter, a load step at the output
can induce ringing at the V
IN
pin. At best, this ringing can
couple to the output and be mistaken as loop instability.
At worst, the ringing at the input can be large enough to
damage the part.
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LTC3407EDD-3#PBF

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Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual, Sync. 800mA 2.25MHz Step-dwn Converter in DFN
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