AT89LS51-16AC Datasheet AT89LS51-16JU, AT89LS51-16PU, AT89LS51-16AU | P13-P15

3053C–MICRO–6/08

AT89LS51

Figure 11-2. External Clock Drive Configuration

12. Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The

mode is invoked by software. The content of the on-chip RAM and all the special function regis-

ters remain unchanged during this mode. The idle mode can be terminated by any enabled

interrupt or by a hardware reset.

Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-

gram execution from where it left off, up to two machine cycles before the internal reset

algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but

access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a

port pin when idle mode is terminated by a reset, the instruction following the one that invokes

idle mode should not write to a port pin or to external memory.

13. Power-down Mode

In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down

is the last instruction executed. The on-chip RAM and Special Function Registers retain their

values until the Power-down mode is terminated. Exit from Power-down mode can be initiated

either by a hardware reset or by activation of an enabled external interrupt (INT0

or INT1). Reset

redefines the SFRs but does not change the on-chip RAM. The reset should not be activated

before V

is restored to its normal operating level and must be held active long enough to allow

the oscillator to restart and stabilize.

XTAL2

XTAL1

GND

EXTERNAL

OSCILLATOR

SIGNAL

Table 13-1. Status of External Pins During Idle and Power-down Modes

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3

Idle Internal 1 1 Data Data Data Data

Idle External 1 1 Float Data Address Data

Power-down Internal 0 0 Data Data Data Data

Power-down External 0 0 Float Data Data Data

3053C–MICRO–6/08

AT89LS51

14. Program Memory Lock Bits

The AT89LS51 has three lock bits that can be left unprogrammed (U) or can be programmed (P)

to obtain the additional features listed in Table 14-1.

When lock bit 1 is programmed, the logic level at the EA

pin is sampled and latched during reset.

If the device is powered up without a reset, the latch initializes to a random value and holds that

value until reset is activated. The latched value of EA

must agree with the current logic level at

that pin in order for the device to function properly.

15. Programming the Flash – Parallel Mode

The AT89LS51 is shipped with the on-chip Flash memory array ready to be programmed. The

programming interface needs a high-voltage (12-volt) program enable signal and is compatible

with conventional third-party Flash or EPROM programmers.

The AT89LS51 code memory array is programmed byte-by-byte.

Programming Algorithm: Before programming the AT89LS51, the address, data, and control

signals should be set up according to the Flash programming mode table (Table 17-1) and Fig-

ure 17-1 and Figure 17-2. To program the AT89LS51, take the following steps:

1. Input the desired memory location on the address lines.

2. Input the appropriate data byte on the data lines.

3. Activate the correct combination of control signals.

4. Raise EA

to 12V.

5. Pulse ALE/PROG

once to program a byte in the Flash array or the lock bits. The byte-

write cycle is self-timed and typically takes no more than 50 µs. Repeat steps 1

through 5, changing the address and data for the entire array or until the end of the

object file is reached.

Data

Polling: The AT89LS51 features Data Polling to indicate the end of a byte write cycle. Dur-

ing a write cycle, an attempted read of the last byte written will result in the complement of the

written data on P0.7. Once the write cycle has been completed, true data is valid on all outputs,

and the next cycle may begin. Data

Polling may begin any time after a write cycle has been

initiated.

Ready/Busy

: The progress of byte programming can also be monitored by the RDY/BSY output

signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY

. P3.0 is

pulled high again when programming is done to indicate READY.

Table 14-1. Lock Bit Protection Modes

Program Lock Bits

LB1 LB2 LB3 Protection Type

1 U U U No program lock features

2PUU

MOVC instructions executed from external program memory

are disabled from fetching code bytes from internal memory,

is sampled and latched on reset, and further

programming of the Flash memory is disabled

3 P P U Same as mode 2, but verify is also disabled

4 P P P Same as mode 3, but external execution is also disabled

3053C–MICRO–6/08

AT89LS51

Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code

data can be read back via the address and data lines for verification. The status of the individ-

ual lock bits can be verified directly by reading them back.

Reading the Signature Bytes: The signature bytes are read by the same procedure as a nor-

mal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7 must be pulled to

a logic low. The values returned are as follows.

(000H) = 1EH indicates manufactured by Atmel

(100H) = 61H indicates 89LS51

(200H) = 06H

Chip Erase: In the parallel programming mode, a chip erase operation is initiated by using the

proper combination of control signals and by pulsing ALE/PROG

low for a duration of 200 ns -

500 ns.

In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase

instruction. In this mode, chip erase is self-timed and takes about 500 ms.

During chip erase, a serial read from any address location will return 00H at the data output.

16. Programming the Flash – Serial Mode

The Code memory array can be programmed using the serial ISP interface while RST is pulled

to V

. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RST is

set high, the Programming Enable instruction needs to be executed first before other operations

can be executed. Before a reprogramming sequence can occur, a Chip Erase operation is

required.

The Chip Erase operation turns the content of every memory location in the Code array into

FFH.

Either an external system clock can be supplied at pin XTAL1 or a crystal needs to be connected

across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than

1/16 of the crystal frequency. With a 16 MHz oscillator clock, the maximum SCK frequency is 1

MHz.

16.1 Serial Programming Algorithm

To program and verify the AT89LS51 in the serial programming mode, the following sequence is

recommended:

1. Power-up sequence:

a. Apply power between VCC and GND pins.

b. Set RST pin to “H”.

If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 16 MHz clock to

XTAL1 pin and wait for at least 10 milliseconds.

2. Enable serial programming by sending the Programming Enable serial instruction to pin

MOSI/P1.5. The frequency of the shift clock supplied at pin SCK/P1.7 needs to be less

than the CPU clock at XTAL1 divided by 16.

3. The Code array is programmed one byte at a time in either the Byte or Page mode. The

write cycle is self-timed and typically takes less than 1 ms at 2.7V.

4. Any memory location can be verified by using the Read instruction that returns the con-

tent at the selected address at serial output MISO/P1.6.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P31

AT89LS51-16AC

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AT89LS51-16AC

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