16
3053C–MICRO–6/08
AT89LS51
5. At the end of a programming session, RST can be set low to commence normal device
operation.
Power-off sequence (if needed):
1. Set XTAL1 to “L” (if a crystal is not used).
2. Set RST to “L”.
3. Turn V
CC
power off.
Data Polling: The Data
Polling feature is also available in the serial mode. In this mode, during
a write cycle an attempted read of the last byte written will result in the complement of the MSB
of the serial output byte on MISO.
16.2 Serial Programming Instruction Set
The Instruction Set for Serial Programming follows a 4-byte protocol and is shown in Table 19-1.
17. Programming Interface – Parallel Mode
Every code byte in the Flash array can be programmed by using the appropriate combination of
control signals. The write operation cycle is self-timed and once initiated, will automatically time
itself to completion.
Most major worldwide programming vendors offer support for the Atmel microcontroller series.
Please contact your local programming vendor for the appropriate software revision.
Notes: 1. Each PROG pulse is 200 ns - 500 ns for Chip Erase.
2. Each PROG
pulse is 200 ns - 500 ns for Write Code Data.
3. Each PROG
pulse is 200 ns - 500 ns for Write Lock Bits.
4. RDY/BSY
signal is output on P3.0 during programming.
5. X = don’t care.
Table 17-1. Flash Programming Modes
Mode V
CC
RST PSEN
ALE/
PROG
EA/
V
PP
P2.6 P2.7 P3.3 P3.6 P3.7
P0.7-0
Data
P2.3-0 P1.7-0
Address
Write Code Data 5V H L
(2)
12V LHHHH D
IN
A11-8 A7-0
Read Code Data 5V H L H H L L L H H D
OUT
A11-8 A7-0
Write Lock Bit 1 5V H L
(3)
12VHHHHH X X X
Write Lock Bit 2 5V H L
(3)
12V H H H L L X X X
Write Lock Bit 3 5V H L
(3)
12V H L H H L X X X
Read Lock Bits
1, 2, 3
5V H L H H H H L H L
P0.2,
P0.3,
P0.4
XX
Chip Erase 5V H L
(1)
12VHLHLL X X X
Read Atmel ID 5V H L H H LLLLL 1EH0000 00H
Read Device ID 5V H L H H LLLLL 61H 0001 00H
Read Device ID 5V H L H H LLLLL 06H 0010 00H
17
3053C–MICRO–6/08
AT89LS51
Figure 17-1. Programming the Flash Memory (Parallel Mode)
Figure 17-2. Verifying the Flash Memory (Parallel Mode)
P1.0-P1.7
P2.6
P3.6
P2.0 - P2.3
A0 - A7
ADDR.
0000H/FFFH
SEE FLASH
PROGRAMMING
MODES TABLE
3 - 16 MHz
P0
P2.7
PGM
DATA
PROG
V/V
IH PP
V
IH
ALE
P3.7
XTAL2 EA
RST
PSEN
XTAL
1
GND
V
CC
AT89S51
P3.3
P3.0
RDY/
BSY
A8 - A11
4.5V - 5.5V
P1.0-P1.7
P2.6
P3.6
P2.0 - P2.3
A0 - A7
ADDR.
0000H/FFFH
SEE FLASH
PROGRAMMING
MODES TABLE
3 - 16 MHz
P0
P2.7
PGM DATA
(USE 10K
PULLUPS)
V
IH
V
IH
ALE
P3.7
XTAL 2 EA
RST
PSEN
XTAL1
GND
V
CC
AT89S51
P3.3
A8 - A11
4.5V - 5.5V
18
3053C–MICRO–6/08
AT89LS51
Figure 18-1. Flash Programming and Verification Waveforms – Parallel Mode
18. Flash Programming and Verification Characteristics (Parallel Mode)
T
A
= 20°C to 30°C, V
CC
= 4.5 to 5.5V
Symbol Parameter Min Max Units
V
PP
Programming Supply Voltage 11.5 12.5 V
I
PP
Programming Supply Current 10 mA
I
CC
V
CC
Supply Current 30 mA
1/t
CLCL
Oscillator Frequency 3 16 MHz
t
AVGL
Address Setup to PROG Low 48 t
CLCL
t
GHAX
Address Hold After PROG 48 t
CLCL
t
DVGL
Data Setup to PROG Low 48 t
CLCL
t
GHDX
Data Hold After PROG 48 t
CLCL
t
EHSH
P2.7 (ENABLE) High to V
PP
48 t
CLCL
t
SHGL
V
PP
Setup to PROG Low 10 µs
t
GHSL
V
PP
Hold After PROG 10 µs
t
GLGH
PROG Width 0.2 1 µs
t
AVQV
Address to Data Valid 48 t
CLCL
t
ELQV
ENABLE Low to Data Valid 48 t
CLCL
t
EHQZ
Data Float After ENABLE 0 48 t
CLCL
t
GHBL
PROG High to BUSY Low 1.0 µs
t
WC
Byte Write Cycle Time 50 µs
t
GLGH
t
GHSL
t
AVGL
t
SHGL
t
DVGL
t
GHAX
t
AVQV
t
GHDX
t
EHSH
t
ELQV
t
WC
BUSY
READY
t
GHBL
t
EHQZ
P1.0 - P1.7
P2.0 - P2.3
ALE/PROG
PORT 0
LOGIC 1
LOGIC 0
EA/V
PP
V
PP
P2.7
(ENABLE)
P3.0
(RDY/BSY)
PROGRAMMING
ADDRESS
VERIFICATION
ADDRESS
DATA I N
DATA OUT

AT89LS51-16AC

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Description:
IC MCU 8BIT 4KB FLASH 44TQFP
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