8304I Data Sheet
©2015 Integrated Device Technology, Inc December 10, 20154
TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, TA = -40°C TO 85°C
TABLE 4A. AC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 166 MHz
tp
LH
Propagation Delay,
Low-to-High; NOTE 1
ƒ 166MHz
2 3.3 ns
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
125MHz,
Integration Range
12kHz – 20MHz
0.17 ps
tsk(o) Output Skew; NOTE 2, 4 ƒ = 133MHz 50 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 600 ps
t
R
Output Rise Time 30% to 70% 250 500 ps
t
F
Output Fall Time 30% to 70% 250 500 ps
odc Output Duty Cycle 40 60 %
NOTE: Electrical parameters are guaranteed over the specifi ed ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airfl ow greater than 500 lfpm. The device will meet
specifi cations after thermal equilibrium has been reached under these conditions.
NOTE: All parameters measured at 166MHz unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defi ned as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2 V
DD
+ 0.3 V
V
IL
Input Low Voltage -0.3 1.3 V
I
IH
Input High Current V
DD
= V
IN
= 3.465V 150 µA
I
IL
Input Low Current V
DD
= 3.465V, V
IN
= 0V -5 µA
V
OH
Output High Voltage; NOTE 1 2.1 V
V
OL
Output Low Voltage; NOTE 1 0.5 V
NOTE 1: Outputs terminated with 50Ω
ΩΩΩ to V
DDO
/2. See Parameter Measurement Section, “3.3V/2.5V Output Load Test Circuit”.
8304I Data Sheet
©2015 Integrated Device Technology, Inc December 10, 20155
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 166 MHz
tp
LH
Propagation Delay, Low-to-High; NOTE 1
ƒ 166MHz
2.3 3.7 ns
tsk(o) Output Skew; NOTE 2, 4 ƒ = 133MHz 60 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 650 ps
t
R
Output Rise Time 30% to 70% 250 500 ps
t
F
Output Fall Time 30% to 70% 250 500 ps
odc Output Duty Cycle 40 60 %
NOTE: Electrical parameters are guaranteed over the specifi ed ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airfl ow greater than 500 lfpm. The device will meet
specifi cations after thermal equilibrium has been reached under these conditions.
All parameters measured at 166MHz unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defi ned as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.
TABLE 4B. AC CHARACTERISTICS, V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, TA = -40°C TO 85°C
8304I Data Sheet
©2015 Integrated Device Technology, Inc December 10, 20156
ADDITIVE PHASE JITTER
The spectral purity in a band at a specifi c offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specifi ed plot in many applications. Phase
noise is defi ned as the ratio of the noise power present in a 1Hz
band at a specifi ed offset from the fundamental frequency to the
power value of the fundamental. This ratio is expressed in decibels
As with most timing specifi cations, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
oor of the equipment is higher than the noise fl oor of the device.
(dBm) or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specifi ed, the phase noise
is called a dBc value, which simply means dBm at a specifi ed offset
from the fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired application
over the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
This is illustrated above. The device meets the noise fl oor of what
is shown, but can actually be lower. The phase noise is dependent
on the input source and measurement equipment.
Additive Phase Jitter @
125MHz (12kHz to 20MHz) = 0.17ps typical

8304AMILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 1-to-4 LVCMOS Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet