Configuration
Table 12. Configuration Features
Feature Description
Dual configuration Stores two configuration images in the configuration flash memory (CFM)
Selects the first configuration image to load using the CONFIG_SEL pin
Design security Supports 128-bit key with non-volatile key programming
Limits access of the JTAG instruction during power-up in the JTAG secure mode
Unique device ID for each Intel MAX 10 device
SEU Mitigation Auto-detects cyclic redundancy check (CRC) errors during configuration
Provides optional CRC error detection and identification in user mode
Dual-purpose configuration
pin
Functions as configuration pins prior to user mode
Provides options to be used as configuration pin or user I/O pin in user mode
Configuration data
compression
Decompresses the compressed configuration bitstream data in real-time during
configuration
Reduces the size of configuration image stored in the CFM
Instant-on Provides the fastest power-up mode for Intel MAX 10 devices.
Table 13. Configuration Schemes for Intel MAX 10 Devices
Configuration Scheme Compression Encryption Dual Image
Configuration
Data Width
Internal Configuration Yes Yes Yes
JTAG 1
Power Management
Table 14. Power Options
Power Options Advantage
Single-supply device Saves board space and costs.
Dual-supply device Consumes less power
Offers higher performance
Power management
controller scheme
Reduces dynamic power consumption when certain applications are in standby mode
Provides a fast wake-up time of less than 1 ms.
Document Revision History for Intel MAX 10 FPGA Device Overview
Date
Version Changes
December 2017 2017.12.15 Added the U324 package for the Intel MAX 10 single power supply
devices.
Updated the 10M02 GPIO and LVDS count in the Maximum Resource
Counts for Intel MAX 10 Devices table.
Updated the I/O vertical migration figure.
February 2017 2017.02.21 Rebranded as Intel.
continued...
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Date Version Changes
December 2016 2016.12.20 Updated EMIF information in the Summary of Features for Intel MAX 10
Devices table. EMIF is only supported in selected Intel MAX 10 device
density and package combinations, and for 600 Mbps performance, –6
device speed grade is required.
Updated the device ordering information to include P for leaded
package.
May 2016 2016.05.02 Removed all preliminary marks.
Update the ADC sampling rate description. The ADC feature monitors
single-ended external inputs with a cumulative sampling rate of 25
kilosamples per second to 1 MSPS in normal mode.
November 2015 2015.11.02 Removed SF feature from the device ordering information figure.
Changed instances of Quartus II to Intel Quartus Prime.
May 2015 2015.05.04 Added clearer descriptions for the feature options listed in the device
ordering information figure.
Updated the maximum dedicated LVDS transmitter count of 10M02
device from 10 to 9.
Removed the F672 package of the Intel MAX 10 10M25 device :
Updated the devices I/O resources per package.
Updated the I/O vertical migration support.
Updated the ADC vertical migration support.
Updated the maximum resources for 10M25 device:
Maximum GPIO from 380 to 360.
Maximum dedicated LVDS transmitter from 26 to 24.
Maximum emulated LVDS transmitter from 181 to 171.
Maximum dedicated LVDS receiver from 181 to 171.
Added ADC information for the E144 package of the 10M04 device.
Updated the ADC vertical migration diagram to clarify that there are
single ADC devices with eight and 16 dual function pins.
Removed the note about contacting Altera for DDR3, DDR3L, DDR2,
and LPDDR2 external memory interface support. The Intel Quartus
Prime software supports these external memory interfaces from version
15.0.
December 2014 2014.12.15 Changed terms:
"dual image" to "dual configuration image"
"dual-image configuration" to dual configuration"
Added memory initialization feature for Flash and Analog devices.
Added maximum data retention capacity of up to 20 years for UFM
feature.
Added maximum operating frequency of 7.25 MHz for serial interface
for UFM feature.
September 2014 2014.09.22 Initial release.
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10M04SCU169I7G

Mfr. #:
Manufacturer:
Intel / Altera
Description:
FPGA - Field Programmable Gate Array non-volatile FPGA, 130 I/O, 169UBGA
Lifecycle:
New from this manufacturer.
Delivery:
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