PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 1 March 2013 8 of 27
NXP Semiconductors
PCA9512A; PCA9512B
Level shifting hot swappable I
2
C-bus and SMBus bus buffer
8.4 Propagation delays
The delay for a rising edge is determined by the combined pull-up current from the bus
resistors and the rise time accelerator current source and the effective capacitance on the
lines. If the pull-up currents are the same, any difference in rise time is directly
proportional to the difference in capacitance between the two sides. The t
PLH
may be
negative if the output capacitance is less than the input capacitance and would be positive
if the output capacitance is larger than the input capacitance, when the currents are the
same.
The t
PHL
can never be negative because the output does not start to fall until the input is
below 0.7V
CC
(or 0.7V
CC2
for SDAOUT and SCLOUT), and the output turn-ON has a
non-zero delay, and the output has a limited maximum slew rate, and even if the input
slew rate is slow enough that the output catches up it will still lag the falling voltage of the
input by the offset voltage. The maximum t
PHL
occurs when the input is driven LOW with
zero delay and the output is still limited by its turn-on delay and the falling edge slew rate.
The output falling edge slew rate is a function of the internal maximum slew rate which is
a function of temperature, V
CC
or V
CC2
and process, as well as the load current and the
load capacitance.
8.5 Rise time accelerators
During positive bus transactions, a 2 mA current source is switched on to quickly slew the
SDA and SCL lines HIGH once the input level of 0.6 V for the PCA9512A is exceeded.
The rising edge rate should be at least 1.25 V/s to guarantee turn on of the accelerators.
The built-in V/t rise time accelerators on all SDA and SCL lines requires the bus pull-up
voltage and respective supply voltage (V
CC
or V
CC2
) to be the same. The built-in V/t
rise time accelerators can be disabled through the ACC pin for lightly loaded systems.
8.6 ACC boost current enable
Users having lightly loaded systems may wish to disable the rise time accelerators.
Driving this pin to ground turns off the rise time accelerators on all four SDAn and SCLn
pins. Driving this pin to the V
CC2
voltage enables normal operation of the rise time
accelerators.
8.7 Resistor pull-up value selection
The system pull-up resistors must be strong enough to provide a positive slew rate of
1.25 V/s on the SDAn and SCLn pins, in order to activate the boost pull-up currents
during rising edges. Choose maximum resistor value using the formula given in
Equation 1
:
(1)
where R
PU
is the pull-up resistor value in , V
CC(min)
is the minimum V
CC
voltage in volts,
and C is the equivalent bus capacitance in picofarads.
R
PU
800 10
3
V
CC min
0.6–
C
-----------------------------------
