PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 1 March 2013 6 of 27
NXP Semiconductors
PCA9512A; PCA9512B
Level shifting hot swappable I
2
C-bus and SMBus bus buffer
In the undervoltage lockout state the connection circuitry is disabled, the rise time
accelerators are disabled, and the precharge circuitry is also disabled. After both V
CC
and
V
CC2
are valid, independent of which is higher, the PCA9512A/B enters the initialization
state; during this state the 1 V precharge circuitry is activated and pulls up the SDAn and
SCLn pins to 1 V through individual 100 k nominal resistors. At the end of the
initialization state the ‘Stop bit and bus idle’ detect circuit is enabled. When all the SDAn
and SCLn pins have been HIGH for the bus idle time or when all pins are HIGH and a
STOP condition is seen on the SDAIN and SCLIN pins, the connect circuitry is activated,
connecting SDAIN to SDAOUT and SCLIN to SCLOUT. The 1 V precharge circuitry is
disabled when the connection is made, unless the ACC pin is LOW; the rise time
accelerators are enabled at this time also.
8.2 Connect circuitry
Once the connection circuitry is activated, the behavior of SDAIN and SDAOUT as well as
SCLIN and SCLOUT become identical, with each acting as a bidirectional buffer that
isolates the input bus capacitance from the output bus capacitance while communicating.
If V
CC
V
CC2
, then a level shifting function is performed between input and output. A LOW
forced on either SDAIN or SDAOUT will cause the other pin to be driven to a LOW by the
PCA9512A/B. The same is also true for the SCLn pins. Noise between 0.7V
CC
and V
CC
on the SDAIN and SCLIN pins, and 0.7V
CC2
and V
CC2
on the SDAOUT and SCLOUT pins
is generally ignored because a falling edge is only recognized when it falls below 0.7V
CC
for SDAIN and SCLIN (or 0.7V
CC2
for SDAOUT and SCLOUT pins) with a slew rate of at
least 1.25 V/s. When a falling edge is seen on one pin, the other pin in the pair turns on a
pull-down driver that is referenced to a small voltage above the falling pin. The driver will
pull the pin down at a slew rate determined by the driver and the load. The first falling pin
may have a fast or slow slew rate; if it is faster than the pull-down slew rate, then the initial
pull-down rate will continue until it is LOW. If the first falling pin has a slow slew rate, then
the second pin will be pulled down at its initial slew rate only until it is just above the first
pin voltage then they will both continue down at the slew rate of the first.
Once both sides are LOW they will remain LOW until all the external drivers have stopped
driving LOWs. If both sides are being driven LOW to the same (or nearly the same) value
by external drivers, which is the case for clock stretching and is typically the case for
acknowledge, and one side external driver stops driving, that pin will rise and rise above
the nominal offset voltage until the internal driver catches up and pulls it back down to the
offset voltage. This bounce is worst for low capacitances and low resistances, and may
become excessive. When the last external driver stops driving a LOW, that pin will bounce
up and settle out just above the other pin as both rise together with a slew rate determined
by the internal slew rate control and the RC time constant. As long as the slew rate is at
least 1.25 V/s, when the pin voltage exceeds 0.6 V, the rise time accelerator circuits are
turned on and the pull-down driver is turned off. If the ACC pin is LOW, the rise time
accelerator circuits will be disabled, but the pull-down driver will still turn off.
8.3 Maximum number of devices in series
Each buffer adds about 0.1 V dynamic level offset at 25 C with the offset larger at higher
temperatures. Maximum offset (V
offset
) is 0.150 V with a 10 k pull-up resistor. The LOW
level at the signal origination end (master) is dependent upon the load and the only
specification point is the I
2
C-bus specification of 3 mA will produce V
OL
< 0.4 V, although if
lightly loaded the V
OL
may be ~0.1 V. Assuming V
OL
= 0.1 V and V
offset
= 0.1 V, the level
after four buffers would be 0.5 V, which is only about 0.1 V below the threshold of the
