6.42
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
17
Depth and Width Expansion
The IDT70V9279/69 features dual chip enables (refer to Truth Table
I) in order to facilitate rapid and simple depth expansion with no require-
ments for external logic. Figure 4 illustrates how to control the varioius chip
enables in order to expand two devices in depth.
The IDT70V9279/69 can also be used in applications requiring
expanded width, as indicated in Figure 4. Since the banks are allocated
at the discretion of the user, the external controller can be set up to drive
the input signals for the various devices as required to allow for 32-bit or
wider applications.
3743 drw 19
IDT70V9279/69
CE0
CE1
CE1
CE0
CE0
CE1
15
14
(1)
CE1
CE0
VDD
VDD
IDT70V9279/69
IDT70V9279/69
IDT70V9279/69
Control Inputs
Control Inputs
Control Inputs
Control Inputs
CNTRST
CLK
ADS
CNTEN
R/W
LB, UB
OE
Figure 4. Depth and Width Expansion with IDT70V9279/69
Functional Description
The IDT70V9279/69 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse is independent of the LOW to HIGH transition of the clock
signal.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to staff the
operation of the address counters for fast interleaved memory applications.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70V9279/69's for depth
expansion configurations. When the Pipelined output mode is enabled, two
cycles are required with CE0 LOW and CE1 HIGH to re-activate the
outputs.
NOTE:
1. A
15 is for IDT70V9279. A14 is for IDT70V9269.
