ACPL-M46T-000E Datasheet ACPL-M46T-000E, ACPL-M46T-500E | P7-P9

LED Drive Circuit Considerations For Ultra High CMR

Performance

Without a detector shield, the dominant cause of op-

tocoupler CMR failure is capacitive coupling from the

input side of the optocoupler, through the package, to

the detector IC as shown in Figure 14. The ACPL-M46T

improves CMR performance by using a detector IC with

an optically transparent Faraday shield, which diverts

the capacitively coupled current away from the sensitive

IC circuitry. However, this shield does not eliminate the

capacitive coupling between the LED and the optocou-

pler output pin and output ground as shown in Figure

15. This capacitive coupling causes perturbations in the

LED current during common mode transients and be-

comes the major source of CMR failures for a shielded

optocoupler. The main design objective of a high CMR

LED drive circuit becomes keeping the LED in the proper

state (on or o ) during common mode transients. For ex-

ample, the recommended application circuit (Figure 13),

can achieve 15 kV/s CMR while minimizing component

complexity. Note that a CMOS gate is recommended in

Figure 13 to keep the LED o when the gate is in the high

state.

Another cause of CMR failure for a shielded optocoupler

is direct coupling to the optocoupler output pins through

LEDO1

in Figure 15. Many factors in uence the e ect and

magnitude of the direct coupling including: the position

of the LED current setting resistor and the value of the

capacitor at the optocoupler output (C

Techniques to keep the LED in the proper state and mini-

mize the e ect of the direct coupling are discussed in the

next two sections.

CMR with the LED on (CMRL)

A high CMR LED drive circuit must keep the LED on dur-

ing common mode transients. This is achieved by over-

driving the LED current beyond the input threshold so

that it is not pulled below the threshold during a tran-

sient. The recommended minimum LED current of 10 mA

provides adequate margin over the maximum I

of 4.0

mA (see Figure 2) to achieve 15 kV/s CMR.

The placement of the LED current setting resistor e ects

the ability of the drive circuit to keep the LED on dur-

ing transients and interacts with the direct coupling to

the optocoupler output. For example, the LED resistor in

Figure 16 is connected to the anode. Figure 17 shows the

AC equivalent circuit for Figure 16 during common mode

transients. During a +dV

/dt in Figure 17, the current

available at the LED anode (Itotal) is limited by the series

resistor. The LED current (I

) is reduced from its DC value

by an amount equal to the current that  ows through

LEDP

and C

LEDO1

. The situation is made worse because the

current through C

LEDO1

has the e ect of trying to pull the

output high (toward a CMR failure) at the same time the

LED current is being reduced. For this reason, the recom-

mended LED drive circuit (Figure 13) places the current

setting resistor in series with the LED cathode. Figure 18

is the AC equivalent circuit for Figure 13 during common

mode transients. In this case, the LED current is not re-

duced during a +dV

/dt transient because the current

 owing through the package capacitance is supplied by

the power supply. During a dV

/dt transient, however,

the LED current is reduced by the amount of current

 owing through CLEDN. But, better CMR performance

is achieved since the current  owing in C

LEDO1

during a

negative transient acts to keep the output low.

CMR with the LED O (CMRH)

A high CMR LED drive circuit must keep the LED o (V

≤ V

F(OFF)

) during common mode transients. For example,

during a +dV

/dt transient in Figure 18, the current

 owing through C

LEDN

is supplied by the parallel combi-

nation of the LED and series resistor. As long as the volt-

age developed across the resistor is less than V

F(OFF)

the

LED will remain o and no common mode failure will oc-

cur. Even if the LED momentarily turns on, the 100 pF ca-

pacitor from pins 5-4 will keep the output from dipping

below the threshold. The recommended LED drive cir-

cuit (Figure 13) provides about 10 V of margin between

the lowest optocoupler output voltage and a 3 V IPM

threshold during a 15kV/s transient with V

= 1500 V.

Additional margin can be obtained by adding a diode

in parallel with the resistor, as shown by the dashed line

connection in Figure 18, to clamp the voltage across the

LED below V

F(OFF)

Since the open collector drive circuit, shown in Figure 19,

cannot keep the LED o during a +dV

/dt transient, it is

not desirable for applications requiring ultra high CMRH

performance. Figure 20 is the AC equivalent circuit for

Figure 19 during common mode transients. Essentially

all the current  owing through CLEDN during a +dV

dt transient must be supplied by the LED. CMRH failures

can occur at dv/dt rates where the current through the

LED and CLEDN exceeds the input threshold. Figure 21 is

an alternative drive circuit which does achieve ultra high

CMR performance by shunting the LED in the o state.

0.80

0.85

0.90

0.95

1.00

1.05

40 -20 0 20 40 60 80 100 120 140

- TEMPERATURE - °C

NORMALIZED OUTPUT CURRENT

0 5 10 15 20

- OUTPUT CURRENT - mA

- FORWARD CURRENT - mA

25°C

125°C

-40°C

=0.6V

= 10mA

= 0.6V

Figure 2. Typical Transfer Characteristics.

Figure 3. Normalized Output Current vs. Temperature.

IPM Dead Time and Propagation Delay Speci cations

The ACPL-M46T includes a Propagation Delay Di erence

speci cation intended to help designers minimize “dead

time” in their power inverter designs. Dead time is the

time period during which both the high and low side

power transistors (Q1 and Q2 in Figure 22) are o . Any

overlap in Q1 and Q2 conduction will result in large cur-

rents  owing through the power devices between the

high and low voltage motor rails.

To minimize dead time the designer must consider the

propagation delay characteristics of the optocoupler as

well as the characteristics of the IPM IGBT gate drive cir-

cuit. Considering only the delay characteristics of the op-

tocoupler (the characteristics of the IPM IGBT gate drive

circuit can be analyzed in the same way) it is important

to know the minimum and maximum turn-on (t

PHL

) and

turn-o (t

PLH

) propagation delay speci cations, prefer-

ably over the desired operating temperature range.

The limiting case of zero dead time occurs when the in-

put to Q1 turns o at the same time that the input to Q2

turns on. This case determines the minimum delay be-

tween LED1 turn-o and LED turn-on, which is related

to the worst case optocoupler propagation delay wave-

forms, as shown in Figure 23. A minimum dead time of

zero is achieved in Figure 23 when the signal to turn on

LED is delayed by (t

PLH max

- t

PHL min

) from the LED1 turn

o . Note that the propagation delays used to calculate

PDD are taken at equal temperatures since the optocou-

plers under consideration are typically mounted in close

proximity to each other. (Speci cally, t

PLH max

and t

PHL min

in the previous equation are not the same as the t

PLH max

and t

PHL min

, over the full operating temperature range,

speci ed in the data sheet.) This delay is the maximum

value for the propagation delay di erence speci cation

which is speci ed at 370 ns for the ACPL-M46T over an

operating temperature range of -40°C to 125°C.

Delaying the LED signal by the maximum propagation

delay di erence ensures that the minimum dead time is

zero, but it does not tell a designer what the maximum

dead time will be. The maximum dead time occurs in

the highly unlikely case where one optocoupler with

the fastest t

PLH

and another with the slowest t

PHL

are in

the same inverter leg. The maximum dead time in this

case becomes the sum of the spread in the t

PLH

and t

PHL

propagation delays as shown in Figure 24. The maximum

dead time is also equivalent to the di erence between

the maximum and minimum propagation delay di er-

ence speci cations. The maximum dead time (due to the

optocouplers) for the ACPL-M46T is 520 ns (= 370 ns -

(-150 ns)) over an operating temperature range of -40°C

to 125°C.

0.1 µF

= 15 V

20 kΩ

SHIELD

F(ON)

=10 mA

OUT

–

*TOTAL LOAD

CAPACITANCE

–

THHL

PHL

PLH

90%

10%

90%

10%

THLH

Figure 5. Input Current vs. Forward Voltage.

Figure 7. CMR Test Circuit.

Figure 6. Propagation Delay Test Circuit.

Typical CMR Waveform.

0.1 µF

=15 V

20 kΩ

SHIELD

OUT

100 pF*

–

*100 pF TOTAL

CAPACITANCE

–

= 1500 V

Δt

SWITCH AT A: I

= 0 mA

SWITCH AT B: I

= 10 mA

Δt

δV

δt

Figure 4. High Level Output Current vs. Temperature.

–

0.00

0.50

1.00

1.50

2.00

-40 -20 0 20 40 60 80 100 120 140

- TEMPERATURE - °C

- HIGH LEVEL OUTPUT CURRENT - uA

=0.8V

= V

= 30V

0.01

0.10

1.00

10.00

100.00

1.20 1.30 1.40 1.50 1.60

- FORWARD VOLTAGE - VOLTS

- FORWARD CURRENT - mA

= 25°C

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

ACPL-M46T-000E

Mfr. #:

Buy ACPL-M46T-000E

Manufacturer:

Broadcom / Avago

Description:

Logic Output Optocouplers 1MBd 30k V/us

Lifecycle:

New from this manufacturer.

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ACPL-M46T-000E

ACPL-M46T-000E

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