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AD2S83IPZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
AD2S83
–9–
REV. E
8. Offset Adjust
Offsets and bias currents at the integrator input can cause an
additional positional offset at the output of the converter of
1 arc minute typical, 5.3 arc minutes maximum. If this can be
tolerated, then R8 and R9 can be omitted from the circuit.
If fitted, the following values of R8 and R9 should be used:
R8 = 4.7 MΩ, R9 = 1 MΩ potentiometer
To adjust the zero offset, ensure the resolver is disconnected
and all the external components are fitted. Connect the
COS pin to the REFERENCE INPUT and the SIN pin to
the SIGNAL GROUND and with the power and reference
applied, adjust the potentiometer to give all “0s” on the
digital output bits.
The potentiometer may be replaced with select on test resistors
if preferred.
DATA TRANSFER
To transfer data the INHIBIT input should be used. The data
will be valid 490 ns after the application of a logic “LO” to the
INHIBIT. This is regardless of the time when the INHIBIT is
applied and allows time for an active BUSY to clear. By using
the ENABLE input the two bytes of data can be transferred
after which the INHIBIT should be returned to a logic “HI”
state to enable the output latches to be updated.
BUSY Output
The validity of the output data is indicated by the state of the
BUSY output. When the input to the converter is changing, the
signal appearing on the BUSY output is a series of pulses at
TTL level. A BUSY pulse is initiated each time the input moves
by the analog equivalent of one LSB and the internal counter is
incremented or decremented.
INHIBIT Input
The INHIBIT logic input only inhibits the data transfer from
the up-down counter to the output latches and, therefore, does
not interrupt the operation of the tracking loop. Releasing the
INHIBIT automatically generates a BUSY pulse to refresh the
output data.
ENABLE Input
The ENABLE input determines the state of the output data. A
logic “HI” maintains the output data pins in the high imped-
ance condition, and the application of a logic “LO” presents the
data in the latches to the output pins. The operation of the
ENABLE has no effect on the conversion process.
BYTE SELECT Input
The BYTE SELECT input selects the byte of the position data
to be presented at the data output DB1 to DB8. The least sig-
nificant byte will be presented on data output DB9 to DB16
(with the ENABLE input taken to a logic “LO”) regardless of
the state of the BYTE SELECT pin. Note that when the AD2S83
is used with a resolution less than 16 bits the unused data lines
are pulled to a logic “LO.” A logic “HI” on the BYTE SELECT
input will present the eight most significant data bits on data
output DB1 and DB8. A logic “LO” will present the least sig-
nificant byte on data outputs 1 to 8, i.e., data outputs 1 to 8 will
duplicate data outputs 9 to 16.
The operation of the BYTE SELECT has no effect on the con-
version process of the converter.
RIPPLE CLOCK
As the output of the converter passes through the major carry,
i.e., all “1s” to all “0s” or the converse, a positive going edge on
the RIPPLE CLOCK (RC) output is initiated indicating that a
revolution, or a pitch, of the input has been completed.
The minimum pulsewidth of the ripple clock is 300 ns. RIPPLE
CLOCK is normally set high before a BUSY pulse and resets
before the next positive going edge of the next BUSY pulse.
The only exception to this is when DIR changes while the
RIPPLE CLOCK is high. Resetting of the RIPPLE clock will
only occur if the DIR remains stable for two consecutive posi-
tive BUSY pulse edges.
If the AD2S83 is being used in a pitch and revolution counting
application, the ripple and busy will need to be gated to prevent
false decrement or increment (see Figure 2).
RIPPLE CLOCK is unaffected by INHIBIT.
5V
5K1
IN4148
BUSY
IN4148
RIPPLE
CLOCK
2N3904
0V
10k 1k
5V
TO COUNTER
(CLOCK)
NOTE: DO NOT USE ABOVE CCT WHEN INHIBIT IS LOW.
Figure 2. Diode Transistor Logic N and Gate
AD2S83
REV. E
–10–
Parameter T
MIN
* T
MAX
* Condition
t
1
150 350 BUSY WIDTH V
H
–V
H
t
2
10 25 RIPPLE CLOCK V
H
to BUSY V
H
t
3
470 580 RIPPLE CLOCK V
L
to Next BUSY V
H
t
4
16 45 BUSY V
H
to DATA V
H
t
5
3 25 BUSY V
H
to DATA V
L
t
6
70 140 INHIBIT V
H
to BUSY V
H
t
7
485 625 MIN DIR V
H
to BUSY V
H
t
8
515 670 MIN DIR V
H
to BUSY V
H
t
9
– 490 INHIBIT V
L
to DATA STABLE
t
10
40 110 ENABLE V
L
to DATA V
H
t
11
35 110 ENABLE V
L
to DATA V
L
t
12
60 140 BYTE SELECT V
L
to DATA STABLE
t
13
60 125 BYTE SELECT V
H
to DATA STABLE
*ns
V
H
BUSY
RIPPLE
CLOCK
DATA
INHIBIT
DIR
INHIBIT
ENABLE
DATA
BYTE
SELECT
DATA
V
H
V
H
V
H
V
H
V
H
V
H
V
H
V
L
V
L
V
L
V
L
V
L
V
L
V
L
V
L
V
Z
t
11
t
10
t
9
t
8
t
7
t
6
t
5
t
4
t
3
t
2
t
1
t
12
t
13
Figure 3. Digital Timing
AD2S83
–11–
REV. E
DIRECTION Output
The DIRECTION (DIR) output indicates the direction of the
input rotation. Any change in the state of DIR precedes the
corresponding BUSY, DATA and RIPPLE CLOCK updates.
DIR can be considered as an asynchronous output and can
make multiple changes in state between two consecutive LSB
update cycles. This occurs when the direction of rotation of the
input changes but the magnitude of the rotation is less than 1 LSB.
COMPLEMENT
The COMPLEMENT input is an active low input and is inter-
nally pulled to +V
S
via 100 kΩ.
Strobing DATA LOAD and COMPLEMENT pins to logic LO
will set the logic HI bits of the AD2S83 counter to a LO state.
Those bits of the applied data which are logic LO will not
change the corresponding bits in the AD2S83 counter.
For Example:
Initial Counter State 1 0 1 0 1
Applied Data Word 1 1 0 0 0
Counter State after DATA LOAD 1 1 0 0 0
Initial Counter State 1 0 1 0 1
Applied Data Word 1 1 0 0 0
Counter State after DATA LOAD and Complement 0 0 1 0 1
In order to read the counter following a DATA LOAD, the
procedure below should be followed:
1. Place outputs in high impedance state (ENABLE = HI).
2. Present data to pins.
3. Pull DATA LOAD and COMPLEMENT pins to ground.
4. Wait 100 ns.
5. Remove data from pins.
6. Remove outputs from high impedance state (ENABLE =
LO).
7. Read outputs.
CIRCUIT FUNCTIONS AND DYNAMIC PERFORMANCE
The AD2S83 allows the user great flexibility in choosing the
dynamic characteristics of the resolver-to-digital conversion to
ensure the optimum system performance. The characteristics
are set by the external components shown in Figure 1. The
Component Selection section explains how to select desired
maximum tracking rate and bandwidth values. The following
paragraphs explain in greater detail the circuit of the AD2S83
and the variations in the dynamic performance available to the
user.
Loop Compensation
The AD2S83 (connected as shown in Figure 1) operates as a
Type 2 tracking servo loop where the VCO/counter combination
and Integrator perform the two integration functions inherent in
a Type 2 loop.
Additional compensation in the form of a pole/zero pair is
required to stabilize the loop.
This compensation is implemented by the integrator compo-
nents (R4, C4, R5, C5).
The overall response the converter is that of a unity gain second
order low-pass filter, with the angle of the resolver as the input
and the digital position data as the output.
The AD2S83 does not have to be connected as tracking con-
verter, parts of the circuit can be used independently. This is
particularly true of the Ratio Multiplier which can be used as a
control transformer. (For more information contact Motion
Control Applications.)
A block diagram of the AD2S83 is given in Figure 4.
RATIO
MULTIPLIER
VCO
PHASE
SENSITIVE
DEMODULATOR
AC ERROR
A, SIN (–) SIN t
SIN SIN t
COS SIN t
DIGITAL
CLOCK
DIRECTION
R4
R5
R6
C5
C4
VELOCITY
INTEGRATOR
Figure 4. Functional Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

AD2S83IPZ-REEL

Mfr. #:
Buy AD2S83IPZ-REEL
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized IC Var Resolution R/D Converter
Lifecycle:
New from this manufacturer.
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