AD2S83
REV. E
–6–
Bit Weight Table
Binary Resolution Degrees Minutes Seconds
Bits (N) (N
N
) /Bit /Bit /Bit
0 1 360.0 21600.0 1296000.0
1 2 180.0 10800.0 648000.0
2 4 90.0 5400.0 324000.0
3 8 45.0 2700.0 162000.0
4 16 22.5 1350.0 81000.0
5 32 11.25 675.0 40500.0
6 64 5.625 337.5 20250.0
7 128 2.8125 168.75 10125.0
8 256 1.40625 84.375 5062.5
9 512 0.703125 42.1875 2531.25
10 1024 0.3515625 21.09375 1265.625
11 2048 0.1757813 10.546875 632.8125
12 4096 0.0878906 5.273438 316.40625
13 8192 0.0439453 2.636719 158.20313
14 16384 0.0219727 1.318359 79.10156
15 32768 0.0109836 0.659180 39.55078
16 65536 0.0054932 0.329590 19.77539
17 131072 0.0027466 0.164795 9.88770
18 262144 0.0013733 0.082397 4.94385
CONNECTING THE CONVERTER
The power supply voltages connected to +V
S
and –V
S
pins
should be +12 V dc and –12 V dc and must not be reversed.
The voltage applied to V
L
can be +5 V dc to +V
S
.
It is recommended that the decoupling capacitors are connected
in parallel between the power lines +V
S
, –V
S
and ANALOG
GROUND adjacent to the converter. Recommended values are
100 nF (ceramic) and 10 µF (tantalum). Also capacitors of
100 nF and 10 µF should be connected between +V
L
and
DIGITAL GROUND adjacent to the converter.
When more than one converter is used on a card, separate de-
coupling capacitors should be used for each converter.
The resolver connections should be made to the SIN and COS
inputs, REFERENCE INPUT and SIGNAL GROUND as
shown in Figure 11 and described in the Connecting the
Resolver section.
The two signal ground wires from the resolver should be joined
at the SIGNAL GROUND pin of the converter to minimize the
coupling between the sine and cosine signals. For this reason it
is also recommended that the resolver is connected using indi-
vidually screened twisted pair cables with the sine, cosine and
reference signals twisted separately.
SIGNAL GROUND and ANALOG GROUND are connected
internally. ANALOG GROUND and DIGITAL GROUND
must be connected externally and as close to the converter as
possible.
The external components required should be connected as
shown in Figure 1.
CONVERTER RESOLUTION
Two major areas of the AD2S83 specification can be selected by
the user to optimize the total system performance. The resolu-
tion of the digital output is set by the logic state of the inputs
SC1 and SC2 to be 10, 12, 14 or 16 bits; and the dynamic char-
acteristics of bandwidth and tracking rate are selected by the
choice of external components.
The choice of the resolution will affect the values of R4 and R6
which scale the inputs to the integrator and the VCO respec-
tively (see Component Selection section). If the resolution is
changed, then new values of R4 and R6 must be switched into
the circuit.
Note: When changing resolution under dynamic conditions, do
it when the BUSY is low, i.e., when data is not changing.
A1
A2
SEGMENT
SWITCHING
RIPPLE
CLOCK
TRACKING
RATE
SELECTION
VELOCITY
SIGNAL
R5
C4
C5
INTEGRATOR
I/P
BANDWIDTH
SELECTION
R8
12V
+12V
OFFSET ADJUST
R9
R3
C3
REFERENCE
I/P
HF FILTER
R2
C2
C1
R1
DEMOD
O/P
PHASE
SENSITIVE
DETECTOR
INTEGRATOR
O/P
DIRECTIONBUSYDIG
GND
16 DATA BITS
SC1
SC2
DATA
LOAD
BYTE
SELECT
5V
+12V
12V
GND
COS
SIG GND
SIN
AC ERROR O/P
AD2S83
VCO
O/P
VCO
I/P
C7
150pF
VCO + DATA
TRANSFER
LOGIC
A3
R4
R7
3K3
C6
390pF
OUTPUT DATA LATCH
R - 2R DAC
16-BIT UP/DOWN COUNTER
R6
INHIBIT
ENABLE
Figure 1. Connection Diagram
AD2S83
–7–
REV. E
CONVERTER OPERATION
When connected in a circuit such as shown in Figure 10, the
AD2S83 operates as a tracking resolver-to-digital converter.
The output will automatically follow the input for speeds up to
the selected maximum tracking rate. No convert command is
necessary as the conversion is automatically initiated by each
LSB increment, or decrement, of the input. Each LSB change of
the converter initiates a BUSY pulse.
The AD2S83 is remarkably tolerant of input amplitude and
frequency variation because the conversion depends only on the
ratio of the input signals. Consequently there is no need for
accurate, stable oscillator to produce the reference signal. The
inclusion of the phase sensitive detector in the conversion loop
ensures high immunity to signals that are not phase or frequency
coherent or are in quadrature with the reference signal.
SIGNAL CONDITIONING
The amplitude of the SINE and COSINE signal inputs should
be maintained within 10% of the nominal values if full perfor-
mance is required from the velocity signal.
The digital position output is relatively insensitive to amplitude
variation. Increasing the input signal levels by more than 10%
will result in a loss in accuracy due to internal overload. Reduc-
ing levels will result in a steady decline in accuracy. With the
signal levels at 50% of the correct value, the angular error will
increase to an amount equivalent to 1.3 LSB. At this level the
repeatability will also degrade to 2 LSB and the dynamic response
will also change, since the dynamic characteristics are propor-
tional to the signal level.
The AD2S83 will not be damaged if the signal inputs are
applied to the converter without the power supplies and/or
the reference.
REFERENCE INPUT
The amplitude of the reference signal applied to the converter’s
input is not critical, but care should be taken to ensure it is kept
within the recommended operating limits.
The AD2S83 will not be damaged if the reference is supplied to
the converter without the power supplies and/or the signal
inputs.
HARMONIC DISTORTION
The amount of harmonic distortion allowable on the signal and
reference lines is 10%.
Square waveforms can be used but the input levels should be
adjusted so that the average value is 1.9 V rms. (For example, a
square wave should be 1.9 V peak.) Triangular and sawtooth
waveforms should have a amplitude of 2 V rms.
Note: The figure specified of 10% harmonic distortion is for
calibration convenience only.
POSITION OUTPUT
The resolver shaft position is represented at the converter out-
put by a natural binary parallel digital word. As the digital posi-
tion output of the converter passes through the major carries,
i.e., all “1s” to all “0s” or the inverse, a RIPPLE CLOCK (RC)
logic output is initiated indicating that a revolution or a pitch of
the input has been completed.
The direction of input rotation is indicated by the DIRECTION
(DIR) logic output. This direction data is always valid in advance
of a RIPPLE CLOCK pulse and, as it is internally latched, only
changing state (1 LSB min change in input) with a correspond-
ing change in direction.
Both the RIPPLE CLOCK pulse and the DIRECTION data
are unaffected by the application of the INHIBIT. The static
positional accuracy quoted is the worst case error that can occur
over the full operating temperature excluding the effects of
offset signals at the INTEGRATOR INPUT (which can be
trimmed out—see Figure 1), and with the following conditions:
input signal amplitudes are within 10% of the nominal; phase
shift between signal and reference is less than 10 degrees.
These operating conditions are selected primarily to establish a
repeatable acceptance test procedure which can be traced to
national standards. In practice, the AD2S83 can be used well
outside these operating conditions providing the above points
are observed.
VELOCITY SIGNAL
The tracking converter technique generates an internal signal at
the output of the integrator (INTEGRATOR OUTPUT) that is
proportional to the rate of change of the input angle. This is a
dc analog output referred to as the VELOCITY signal.
It is recommended that the velocity output be buffered.
The sense is positive for an increasing angular input and nega-
tive for decreasing angular input. The full-scale velocity output
is ±8 V dc. The output velocity scaling and tracking rate are a
function of the resolution of the converter; this is summarized
below.
Max Tracking Nominal Scaling
Res Rate (rps) (rps/V dc)
10 1040 130
12 260 32.5
14 65 8.125
16 16.25 2.03
(Velocity O/P = ±8 V dc nominal)
The output velocity can be suitably scaled and used to replace a
conventional DC tachogenerator. For more detailed information
see the AD2S83 as a Silicon Tachogenerator section.
DC ERROR SIGNAL
The signal at the output of the phase sensitive detector
(DEMODULATOR OUTPUT) is the signal to be nulled by
the tracking loop and is, therefore, proportional to the error
between the input angle and the output digital angle. As the
converter is a Type 2 servo loop, the demodulator output signal
will increase if the output fails to track the input for any reason.
This is an indication that the input has exceeded the maximum
tracking rate of the converter or, due to some internal or exter-
nal malfunction, the converter is unable to reach a null. By con-
necting two external comparators, this voltage can be used as a
“built-in-test.”
AD2S83
REV. E
–8–
COMPONENT SELECTION
The following instructions describe how to select the external
components for the converter in order to achieve the required
bandwidth and tracking rate. In all cases the nearest “preferred
value” component should be used, and a 5% tolerance will not
degrade the overall performance of the converter. Care should
be taken that the resistors and capacitors will function over the
required operating temperature range. The components should
be connected as shown in Figure 1.
Free PC compatible software is available to help users select the
optimum component values for the AD2S83, and display the transfer
gain, phase and small step response.
For more detailed information and explanation, see the Circuit
Functions and Dynamic Performance section.
1. HF Filter (R1, R2, C1, C2)
The function of the HF filter is to remove any dc offset and
to reduce the amount of noise present on the signal inputs to
the AD2S83, reaching the Phase Sensitive Detector and
affecting the outputs. R1 and C2 may be omitted—in which
case R2 = R3 and C1 = C3, calculated below—but their use
is particularly recommended if noise from switch mode
power supplies and brushless motor drive is present.
Values should be chosen so that
15 kΩ≤R1= R2 56 k
C1= C2 =
1
2 π R1 f
REF
and f
REF
= Reference Frequency (Hz)
This filter gives an attenuation of three times at the input to
the phase sensitive detector.
2. Gain Scaling Resistor (R4) (See Phase Sensitive Demodula-
tor section.)
If R1, C2 are used:
R4 =
E
DC
100 × 10
9
×
1
3
where 100 × 10
9
= current/LSB
If R1, C2 are not used:
R4 =
E
DC
100 × 10
9
where E
DC
= 160 × 10
3
for 10 bits resolution
= 40 × 10
3
for 12 bits
= 10 × 10
3
for 14 bits
= 2.5 × 10
3
for 16 bits
= Scaling of the DC ERROR in volts/LSB
3. AC Coupling of Reference Input (R3, C3)
Select R3 and C3 so that there is no significant phase shift at
the reference frequency. That is,
R3 = 100 k
C 3 >
1
R3 × f
REF
F
with R3 in .
4. Maximum Tracking Rate (R6)
The VCO input resistor R6 sets the maximum tracking rate
of the converter and hence the velocity scaling as at the max
tracking rate, the velocity output will be 8 V.
Decide on your maximum tracking rate, T, in revolutions
per second. When setting the value for R6, it should be
remembered that the linearity of the velocity output is
specified across 0 kHz500 kHz and 500 kHz1000 kHz.
The following conversion can be used to determine the
corresponding rps:
rps =
VCO Rate (Hz )
2
N
Note that T must not exceed the maximum tracking rate
or 1/16 of the reference frequency.
R6 =
6.81 × 10
10
T × n
where n = bits per revolution
= 1,024 for 10 bits resolution
= 4,096 for 12 bits
= 16,384 for 14 bits
= 65,536 for 16 bits
5. Closed-Loop Bandwidth Selection (C4, C5, R5)
a. Choose the closed-loop bandwidth (f
BW
) required
ensuring that the ratio of reference frequency to band-
width does not exceed the following guidelines:
Resolution Ratio of Reference Frequency/Bandwidth
10 2.5 : 1
12 4 : 1
14 6 : 1
16 7.5 : 1
Typical values may be 100 Hz for a 400 Hz reference fre-
quency and 500 Hz to 1000 Hz for a 5 kHz reference
frequency.
b. Select C4 so that
C4 =
21
R6 × f
BW
2
F
with R6 in and f
BW
, in Hz selected above.
c. C5 is given by
C5 = 5 × C4
d. R5 is given by
R5 =
4
2 ×π× f
BW
× C5
6. VCO Phase Compensation
The following values of C6 and R7 should be connected as
close as possible to the VCO output, Pin 41.
C6 = 390 pF, R7 = 3. 3 k
7. VCO Optimization
To optimize the performance of the VCO a capacitor, C7,
should be placed across the VCO input and output, Pins 40
and 41.
C7 = 150 pF

AD2S83IPZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized IC Var Resolution R/D Converter
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet