RT8023
15
DS8023-03 March 2011 www.richtek.com
The output ripple will be highest at maximum input voltage
since ΔI
L
increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and
RMS current handling requirement. Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Special polymer
capacitors offer very low ESR value. However, it provides
lower capacitance density than other types. Although
Tantalum capacitors have the highest capacitance density,
it is important to only use types that pass the surge test
for use in switching power supplies. Aluminum electrolytic
capacitors have significantly higher ESR. However, it can
be used in cost-sensitive applications for ripple current
rating and long term reliability considerations. Ceramic
capacitors have excellent low ESR characteristics but can
have a high voltage coefficient and audible piezoelectric
effects. The high Q of ceramic capacitors with trace
inductance can also lead to significant ringing.
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input, V
IN
. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at V
IN
large enough to damage the
part.
Output Voltage Programming
The resistive divider allows the FB pin to sense a fraction
of the output voltage as shown in Figure2.
RT8023
GND
FB
R1
R2
V
OUT
Figure 2. Setting the Output Voltage
For adjustable voltage mode, the output voltage is set by
an external resistive divider according to the following
equation :
OUT REF
R1
V = V 1
R2
⎛⎞
+
⎜⎟
⎝⎠
Where V
REF
is the internal reference voltage (0.8V typ.).
Efficiency Consideration
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. The efficiency can be expressed
as :
Efficiency = 100 − (L1 + L2 + L3 + …..)
Where L1, L2, etc., are the individual losses as a
percentage of input power, although all dissipative
elements in the circuit produce losses, V
IN
quiescent
current and I
2
R losses are two main sources for most of
the losses.
The V
IN
quiescent current loss dominates the efficiency
loss at a very low load current whereas the I
2
R loss
dominates the efficiency loss at medium to high load
current. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence.
1. The V
IN
quiescent current appears due to two factors
including the DC bias current as given in the electrical
characteristics and the internal main switch and
synchronous switch gate charge currents. The gate charge
current results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of charge
ΔQ moves from V
IN
to ground.
The value of ΔQ/Δt is the current out of V
IN
that is typically
larger than the DC bias current. In continuous mode,
I
GATECHG
= f(Q
T
+ Q
B
)
Where Q
T
and Q
B
are the gate charges of the internal top
and bottom switches. Both the DC bias and gate charge
losses are proportional to V
IN
and their effects will be more
significant at higher supply voltages.
