RT8023
16
DS8023-03 March 2011www.richtek.com
2. I
2
R losses are calculated from the resistance of the
internal switches R
SW
and external inductor R
L
. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main switch
and the synchronous switch. Thus, the series resistance
looking into the LX pin is a function of both top and bottom
MOSFETs R
DS(ON)
and the duty cycle (DC) as follows :
R
SW
= R
DS(ON)TOP
x DC + R
DS(ON)BOT
x (1−DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristic
curves. Thus, to obtain I
2
R loss, simply add R
SW
to R
L
and multiply the result by the square of the average output
current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% of total losses.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to ΔI
LOAD
(ESR) also begins to charge or discharge
C
OUT
generating a feedback error signal for the regulator
to return V
OUT
to its steady-state value. During this recovery
time, V
OUT
can be monitored for overshoot or ringing that
would indicate a stability problem.
For LDO Part
The external capacitors used with the RT8023 must be
carefully selected for regulator stability and performance
just like any low-dropout regulator.
Using a capacitor whose value is >1μF on the RT8023
input and the amount of capacitance can be increased
without limit. The input capacitor must be located at a
distance of not more than 1cm from the input pin of the IC
and returned to a clean analog ground. Any good quality
ceramic or tantalum can be used for this capacitor. The
capacitor with larger value and lower ESR (equivalent series
resistance) provides better PSRR and line-transient
response.
The output capacitor must meet both requirements for
minimum amount of capacitance and ESR in all LDO
applications. The RT8023 is designed specifically to work
with low ESR ceramic output capacitor for space-saving
and performance consideration.
Enable
The RT8023 goes into sleep mode when the EN pin is in
the logic low condition. The RT8023 has an EN pin to turn
on or turn off the regulator during this condition. When
the EN pin is in the logic high condition, the regulator will
be turned on. The typical supply current for the EN pin is
0.1μA. The EN pin may be directly tied to V
IN
to keep the
part on. The enable input is CMOS logic and can not be
left floating.
Current Limit
The RT8023 contains an independent current limiter to
monitor and control the pass transistor's gate voltage. The
part limits the two LDOs' current respectively as follows :
LDO1 : 700mA and LDO2 : 350mA (min.). The output can
be shorted to ground indefinitely without damaging the
part.
PGOOD
The power good output is an open-drain output. It is
designed essentially to work as a power-on reset generator
once the regulated voltage was up or a fault condition
occurs. The output of the power good drives to low when
a fault condition occurs. The power good output will be
driven back to up once the output reaches 90% of its
nominal value. The output voltage level will be drooped at
the fault condition including current limit, thermal shutdown
or shutdown and triggers the PGOOD detector to alarm a
fault condition.
Due to the shutdown mode condition, a fault condition
occurs by pulling up the PGOOD output low. And it will
sink a current from the open drain and the external power.
It is recommended to select a suitable pulling resistance
to achieve the goal of ideal power dissipation control.
PSRR
The power supply rejection ratio (PSRR) is defined as the
ability of a regulator to maintain its output voltage as its
power supply voltage is varied. The PSRR is found to be:
PSRR = 20 x log[ ΔV
OUT
/ΔV
IN
]
