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74HCT574N,652

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
74HC_HCT574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 7 of 19
NXP Semiconductors
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 10.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC574
t
pd
propagation
delay
CP to Qn; see Figure 7
[1]
V
CC
= 2.0 V - 47 150 - 190 - 225 ns
V
CC
= 4.5 V - 17 30 - 35 - 45 ns
V
CC
=5V; C
L
=15pF - 14 - - - - - ns
V
CC
= 6.0 V - 14 26 - 33 - 38 ns
t
en
enable time OE to Qn; see Figure 9
[2]
V
CC
= 2.0 V - 44 140 - 175 - 210 ns
V
CC
= 4.5 V - 16 28 - 35 - 42 ns
V
CC
= 6.0 V - 13 24 - 30 - 36 ns
t
dis
disable time OE to Qn; see Figure 9
[3]
V
CC
= 2.0 V - 39 125 - 155 - 190 ns
V
CC
= 4.5 V - 14 25 - 31 - 38 ns
V
CC
= 6.0 V - 11 21 - 26 - 32 ns
t
t
transition
time
Qn; see Figure 7
[4]
V
CC
= 2.0 V - 14 60 - 75 - 90 ns
V
CC
= 4.5 V - 5 12 - 15 - 18 ns
V
CC
= 6.0 V - 4 10 - 13 - 15 ns
t
W
pulse width CP HIGH or LOW;
see Figure 8
V
CC
= 2.0 V 80 14 - 100 - 120 - ns
V
CC
= 4.5 V 16 5 - 20 - 24 - ns
V
CC
= 6.0 V 14 4 - 17 - 20 - ns
t
su
set-up time Dn to CP; see Figure 8
V
CC
= 2.0 V 60 6 - 75 - 90 - ns
V
CC
= 4.5 V 12 2 - 15 - 18 - ns
V
CC
= 6.0 V 10 2 - 13 - 15 - ns
t
h
hold time Dn to CP; see Figure 8
V
CC
= 2.0 V 5 0 - 5 - 5 - ns
V
CC
= 4.5 V 5 0 - 5 - 5 - ns
V
CC
= 6.0 V 5 0 - 5 - 5 - ns
f
max
maximum
frequency
CP; see Figure 7
V
CC
= 2.0 V 6.0 37 - 4.8 - 4.0 - MHz
V
CC
= 4.5 V 30 112 - 24 - 20 - MHz
V
CC
=5V; C
L
= 15 pF - 123 - - - - - MHz
V
CC
= 6.0 V 35 133 - 28 - 24 - MHz
74HC_HCT574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 8 of 19
NXP Semiconductors
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
[1] t
pd
is the same as t
PLH
and t
PHL
.
[2] t
en
is the same as t
PZH
and t
PZL
.
[3] t
dis
is the same as t
PLZ
and t
PHZ
.
[4] t
t
is the same as t
THL
and t
TLH
.
[5] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of outputs.
C
PD
power
dissipation
capacitance
C
L
=50pF;f=1 MHz;
V
I
=GNDtoV
CC
[5]
-22- - - - -pF
74HCT574
t
pd
propagation
delay
CP to Qn; see Figure 7
[1]
V
CC
= 4.5 V - 18 33 - 41 - 50 ns
V
CC
=5V; C
L
=15pF - 15 - - - - - ns
t
en
enable time OE to Qn; see Figure 9
[2]
V
CC
= 4.5 V - 19 33 - 41 - 50 ns
t
dis
disable time OE to Qn; see Figure 9
[3]
V
CC
= 4.5 V - 16 28 - 35 - 42 ns
t
t
transition
time
Qn; see Figure 7
[4]
V
CC
= 4.5 V - 5 12 - 15 - 18 ns
t
W
pulse width CP HIGH or LOW;
see Figure 8
V
CC
= 4.5 V 16 7 - 20 - 24 - ns
t
su
set-up time Dn to CP; see Figure 8
V
CC
= 4.5 V 12 3 - 15 - 18 - ns
t
h
hold time Dn to CP; see Figure 8
V
CC
= 4.5 V 5 1- 5 - 5 - ns
f
max
maximum
frequency
CP; see Figure 7
V
CC
= 4.5 V 30 69 - 24 - 20 - MHz
V
CC
=5V; C
L
=15pF - 76 - - - - - MHz
C
PD
power
dissipation
capacitance
C
L
=50pF;f=1 MHz;
V
I
=GNDtoV
CC
1.5 V
[5]
-25- - - - -pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 10.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC_HCT574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 26 January 2015 9 of 19
NXP Semiconductors
74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
11. Waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 7. Propagation delay input (CP) to output (Qn), output transition time, clock input (CP) pulse width and the
maximum frequency (CP)
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 8. The data input (D) to clock input (CP) set-up times and clock input (CP) to data input (D) hold times
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

74HCT574N,652

Mfr. #:
Buy 74HCT574N,652
Manufacturer:
NXP Semiconductors
Description:
Flip Flops OCTAL D F/F POS-EDGE 3STATE
Lifecycle:
New from this manufacturer.
Delivery:
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