P3PS550AH
http://onsemi.com
2
VSS
VDD
CLKIN
ModOUT
PLL
SR0
SR1
SR2
PD#
Figure 1. Block Diagram
P3PS550AH modulates the output of a single PLL in
order to “spread” the bandwidth of a synthesized clock, and
more importantly, decreases the peak amplitudes of its
harmonics. This results in significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most frequency generators. Lowering EMI
by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’.
P3PS550AH accepts an input from an external reference
clock and locks to a 1x modulated clock output. SR0, SR1
and SR2 pins enable selecting one of the eight different
frequency deviations (Refer Frequency Deviation Selection
table). P3PS550AH also features power down option for
power save. P3PS550AH operates over a supply voltage
range of 2.3 V to 3.6 V. P3PS550AH is available in an 8 Pin
WDFN, (2 mm x 2 mm) Package.
Table 1. PIN DESCRIPTION
Pin# Pin Name Type Description
1 CLKIN I External reference clock input.
2 SR2 I Digital logic input used to select Spreading Range. There is NO default state.
Refer Frequency Deviation Selection Table.
3 PD# I Power−down control pin. Powers down the entire chip. There is NO default state. Pull low to en-
able power−down mode. Connect to VDD to disable Power Down.
Output Clock will be LOW when power down is enabled
4 VSS P Ground connection.
5 ModOUT O Spread Spectrum Clock Output.
6 SR1 I Digital logic input used to select Spreading Range. This pin has an internal pull−up resistor. Refer
Modulation Selection Table.
7 SR0 I Digital logic input used to select Spreading Range. There is NO default state.
Refer Frequency Deviation Selection Table.
8 VDD P Power supply for the entire chip
